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From bb7dfcf9824a48cbde67bbf4f5180f8901a7373d Mon Sep 17 00:00:00 2001 |
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From: Sasha Levin <sashal@kernel.org> |
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Date: Thu, 20 Oct 2022 11:46:44 -0400 |
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Subject: drm/amd/display: Limit dcn32 to 1950Mhz display clock |
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From: Jun Lei <jun.lei@amd.com> |
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[ Upstream commit e59843c4cdd68a369591630088171eeacce9859f ] |
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[why] |
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Hardware team recommends we limit dispclock to 1950Mhz for all DCN3.2.x |
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[how] |
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Limit to 1950 when initializing clocks. |
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Tested-by: Mark Broadworth <mark.broadworth@amd.com> |
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Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> |
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Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> |
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Signed-off-by: Jun Lei <jun.lei@amd.com> |
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
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Cc: stable@vger.kernel.org # 6.0.x |
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Signed-off-by: Sasha Levin <sashal@kernel.org> |
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--- |
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.../gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 8 ++++---- |
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1 file changed, 4 insertions(+), 4 deletions(-) |
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diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c |
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index f4c7bbd9961a..f3090ead9af5 100644 |
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--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c |
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+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c |
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@@ -157,6 +157,7 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base) |
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struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); |
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unsigned int num_levels; |
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struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk; |
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+ unsigned int i; |
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|
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memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks)); |
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clk_mgr_base->clks.p_state_change_support = true; |
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@@ -205,18 +206,17 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base) |
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clk_mgr->dpm_present = true; |
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if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) { |
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- unsigned int i; |
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- |
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for (i = 0; i < num_levels; i++) |
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if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz |
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< khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz)) |
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clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz |
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= khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz); |
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} |
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+ for (i = 0; i < num_levels; i++) |
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+ if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz > 1950) |
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+ clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz = 1950; |
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|
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if (clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz) { |
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- unsigned int i; |
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- |
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for (i = 0; i < num_levels; i++) |
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if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz |
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< khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz)) |
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-- |
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2.35.1 |
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