current/SOURCES/drm-amd-display-set-memclk-levels-to-be-at-least-1-f.patch

From 4192cd9a4e3bf4b8c067d7820c5ed6112b780577 Mon Sep 17 00:00:00 2001
From: Sasha Levin <sashal@kernel.org>
Date: Thu, 20 Oct 2022 11:46:48 -0400
Subject: drm/amd/display: Set memclk levels to be at least 1 for dcn32

From: Dillon Varone <Dillon.Varone@amd.com>

[ Upstream commit 6cb5cec16c380be4cf9776a8c23b72e9fe742fd1 ]

[Why]
Cannot report 0 memclk levels even when SMU does not provide any.

[How]
When memclk levels reported by SMU is 0, set levels to 1.

Tested-by: Mark Broadworth <mark.broadworth@amd.com>
Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 6.0.x
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index f3090ead9af5..e7f1d5f8166f 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -667,6 +667,9 @@ static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
                        &clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz,
                        &num_entries_per_clk->num_memclk_levels);
 
+       /* memclk must have at least one level */
+       num_entries_per_clk->num_memclk_levels = num_entries_per_clk->num_memclk_levels ? num_entries_per_clk->num_memclk_levels : 1;
+
        dcn32_init_single_clock(clk_mgr, PPCLK_FCLK,
                        &clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz,
                        &num_entries_per_clk->num_fclk_levels);
-- 
2.35.1

1	From 4192cd9a4e3bf4b8c067d7820c5ed6112b780577 Mon Sep 17 00:00:00 2001
2	From: Sasha Levin <sashal@kernel.org>
3	Date: Thu, 20 Oct 2022 11:46:48 -0400
4	Subject: drm/amd/display: Set memclk levels to be at least 1 for dcn32
5
6	From: Dillon Varone <Dillon.Varone@amd.com>
7
8	[ Upstream commit 6cb5cec16c380be4cf9776a8c23b72e9fe742fd1 ]
9
10	[Why]
11	Cannot report 0 memclk levels even when SMU does not provide any.
12
13	[How]
14	When memclk levels reported by SMU is 0, set levels to 1.
15
16	Tested-by: Mark Broadworth <mark.broadworth@amd.com>
17	Reviewed-by: Martin Leung <Martin.Leung@amd.com>
18	Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
19	Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
20	Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
21	Cc: stable@vger.kernel.org # 6.0.x
22	Signed-off-by: Sasha Levin <sashal@kernel.org>
23	---
24	drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c \| 3 +++
25	1 file changed, 3 insertions(+)
26
27	diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
28	index f3090ead9af5..e7f1d5f8166f 100644
29	--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
30	+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
31	@@ -667,6 +667,9 @@ static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
32	&clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz,
33	&num_entries_per_clk->num_memclk_levels);
34
35	+ /* memclk must have at least one level */
36	+ num_entries_per_clk->num_memclk_levels = num_entries_per_clk->num_memclk_levels ? num_entries_per_clk->num_memclk_levels : 1;
37	+
38	dcn32_init_single_clock(clk_mgr, PPCLK_FCLK,
39	&clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz,
40	&num_entries_per_clk->num_fclk_levels);
41	--
42	2.35.1
43