/[packages]/cauldron/kernel/current/PATCHES/patches/0024-mmc-sdhci-pci-o2micro-Add-quirk-for-O2-Micro-dev-0x8.patch
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Contents of /cauldron/kernel/current/PATCHES/patches/0024-mmc-sdhci-pci-o2micro-Add-quirk-for-O2-Micro-dev-0x8.patch

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Revision 1329221 - (show annotations) (download)
Fri Nov 9 22:05:45 2018 UTC (5 years, 9 months ago) by tmb
File size: 2573 byte(s)
add fixes from sashas autosel queue
1 From d46d9cd0aff70bb9e8b659a898c11a60a30e0a99 Mon Sep 17 00:00:00 2001
2 From: Yu Zhao <yuzhao@google.com>
3 Date: Sun, 23 Sep 2018 14:39:24 -0600
4 Subject: [PATCH 024/145] mmc: sdhci-pci-o2micro: Add quirk for O2 Micro dev
5 0x8620 rev 0x01
6
7 [ Upstream commit 5169894982bb67486d93cc1e10151712bb86bcb6 ]
8
9 This device reports SDHCI_CLOCK_INT_STABLE even though it's not
10 ready to take SDHCI_CLOCK_CARD_EN. The symptom is that reading
11 SDHCI_CLOCK_CONTROL after enabling the clock shows absence of the
12 bit from the register (e.g. expecting 0x0000fa07 = 0x0000fa03 |
13 SDHCI_CLOCK_CARD_EN but only observed the first operand).
14
15 mmc1: Timeout waiting for hardware cmd interrupt.
16 mmc1: sdhci: ============ SDHCI REGISTER DUMP ===========
17 mmc1: sdhci: Sys addr: 0x00000000 | Version: 0x00000603
18 mmc1: sdhci: Blk size: 0x00000000 | Blk cnt: 0x00000000
19 mmc1: sdhci: Argument: 0x00000000 | Trn mode: 0x00000000
20 mmc1: sdhci: Present: 0x01ff0001 | Host ctl: 0x00000001
21 mmc1: sdhci: Power: 0x0000000f | Blk gap: 0x00000000
22 mmc1: sdhci: Wake-up: 0x00000000 | Clock: 0x0000fa03
23 mmc1: sdhci: Timeout: 0x00000000 | Int stat: 0x00000000
24 mmc1: sdhci: Int enab: 0x00ff0083 | Sig enab: 0x00ff0083
25 mmc1: sdhci: AC12 err: 0x00000000 | Slot int: 0x00000000
26 mmc1: sdhci: Caps: 0x25fcc8bf | Caps_1: 0x00002077
27 mmc1: sdhci: Cmd: 0x00000000 | Max curr: 0x005800c8
28 mmc1: sdhci: Resp[0]: 0x00000000 | Resp[1]: 0x00000000
29 mmc1: sdhci: Resp[2]: 0x00000000 | Resp[3]: 0x00000000
30 mmc1: sdhci: Host ctl2: 0x00000008
31 mmc1: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x00000000
32 mmc1: sdhci: ============================================
33
34 The problem happens during wakeup from S3. Adding a delay quirk
35 after power up reliably fixes the problem.
36
37 Signed-off-by: Yu Zhao <yuzhao@google.com>
38 Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
39 Signed-off-by: Sasha Levin <sashal@kernel.org>
40 ---
41 drivers/mmc/host/sdhci-pci-o2micro.c | 3 +++
42 1 file changed, 3 insertions(+)
43
44 diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c
45 index 77e9bc4aaee9..cc3ffeffd7a2 100644
46 --- a/drivers/mmc/host/sdhci-pci-o2micro.c
47 +++ b/drivers/mmc/host/sdhci-pci-o2micro.c
48 @@ -490,6 +490,9 @@ int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
49 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
50 break;
51 case PCI_DEVICE_ID_O2_SEABIRD0:
52 + if (chip->pdev->revision == 0x01)
53 + chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
54 + /* fall through */
55 case PCI_DEVICE_ID_O2_SEABIRD1:
56 /* UnLock WP */
57 ret = pci_read_config_byte(chip->pdev,
58 --
59 2.19.1
60

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