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From 35029d4361809cf5c04eea442b617eaf08cd89fd Mon Sep 17 00:00:00 2001 |
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From: Plamena Manolova <plamena.manolova@intel.com> |
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Date: Tue, 12 Mar 2019 21:25:36 +0200 |
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Subject: [PATCH 09/22] i965: Disable ARB_fragment_shader_interlock for |
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platforms prior to GEN9 |
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|
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ARB_fragment_shader_interlock depends on memory fences to |
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ensure fragment ordering and this ordering guarantee is |
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only supported from GEN9 onwards. |
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|
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Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109980 |
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Fixes: 939312702e35 "i965: Add ARB_fragment_shader_interlock support." |
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Signed-off-by: Plamena Manolova <plamena.n.manolova@gmail.com> |
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Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> |
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(cherry picked from commit 19ab08200179e71af42ce6e1b91f502e50f915b3) |
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--- |
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src/intel/compiler/brw_fs_generator.cpp | 1 + |
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src/mesa/drivers/dri/i965/intel_extensions.c | 25 +++++++++++++++++++- |
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2 files changed, 25 insertions(+), 1 deletion(-) |
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|
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diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp |
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index fb77ece30ca..09382775f3e 100644 |
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--- a/src/intel/compiler/brw_fs_generator.cpp |
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+++ b/src/intel/compiler/brw_fs_generator.cpp |
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@@ -2100,6 +2100,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) |
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break; |
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|
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case SHADER_OPCODE_INTERLOCK: |
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+ assert(devinfo->gen >= 9); |
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/* The interlock is basically a memory fence issued via sendc */ |
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brw_memory_fence(p, dst, BRW_OPCODE_SENDC); |
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break; |
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diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c |
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index a9730ba66fe..92ecd612006 100644 |
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--- a/src/mesa/drivers/dri/i965/intel_extensions.c |
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+++ b/src/mesa/drivers/dri/i965/intel_extensions.c |
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@@ -253,7 +253,6 @@ intelInitExtensions(struct gl_context *ctx) |
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ctx->Extensions.EXT_shader_samples_identical = true; |
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ctx->Extensions.OES_primitive_bounding_box = true; |
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ctx->Extensions.OES_texture_buffer = true; |
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- ctx->Extensions.ARB_fragment_shader_interlock = true; |
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|
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if (can_do_pipelined_register_writes(brw->screen)) { |
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ctx->Extensions.ARB_draw_indirect = true; |
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@@ -318,6 +317,30 @@ intelInitExtensions(struct gl_context *ctx) |
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ctx->Extensions.KHR_blend_equation_advanced_coherent = true; |
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ctx->Extensions.KHR_texture_compression_astc_ldr = true; |
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ctx->Extensions.KHR_texture_compression_astc_sliced_3d = true; |
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+ |
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+ /* |
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+ * From the Skylake PRM Vol. 7 (Memory Fence Message, page 221): |
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+ * "A memory fence message issued by a thread causes further messages |
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+ * issued by the thread to be blocked until all previous data port |
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+ * messages have completed, or the results can be globally observed from |
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+ * the point of view of other threads in the system." |
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+ * |
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+ * From the Haswell PRM Vol. 7 (Memory Fence, page 256): |
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+ * "A memory fence message issued by a thread causes further messages |
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+ * issued by the thread to be blocked until all previous messages issued |
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+ * by the thread to that data port (data cache or render cache) have |
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+ * been globally observed from the point of view of other threads in the |
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+ * system." |
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+ * |
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+ * Summarized: For ARB_fragment_shader_interlock to work, we need to |
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+ * ensure memory access ordering for all messages to the dataport from |
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+ * all threads. Memory fence messages prior to SKL only provide memory |
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+ * access ordering for messages from the same thread, so we can only |
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+ * support the feature from Gen9 onwards. |
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+ * |
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+ */ |
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+ |
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+ ctx->Extensions.ARB_fragment_shader_interlock = true; |
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} |
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|
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if (gen_device_info_is_9lp(devinfo)) |
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-- |
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2.21.0 |
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|