/[packages]/cauldron/mesa/current/SOURCES/0009-i965-Disable-ARB_fragment_shader_interlock-for-platf.patch
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Contents of /cauldron/mesa/current/SOURCES/0009-i965-Disable-ARB_fragment_shader_interlock-for-platf.patch

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Revision 1379265 - (show annotations) (download)
Wed Mar 20 17:08:42 2019 UTC (2 months ago) by tmb
File size: 3684 byte(s)
more fixes from staging/19.0 branch
1 From 35029d4361809cf5c04eea442b617eaf08cd89fd Mon Sep 17 00:00:00 2001
2 From: Plamena Manolova <plamena.manolova@intel.com>
3 Date: Tue, 12 Mar 2019 21:25:36 +0200
4 Subject: [PATCH 09/24] i965: Disable ARB_fragment_shader_interlock for
5 platforms prior to GEN9
6
7 ARB_fragment_shader_interlock depends on memory fences to
8 ensure fragment ordering and this ordering guarantee is
9 only supported from GEN9 onwards.
10
11 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109980
12 Fixes: 939312702e35 "i965: Add ARB_fragment_shader_interlock support."
13 Signed-off-by: Plamena Manolova <plamena.n.manolova@gmail.com>
14 Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
15 (cherry picked from commit 19ab08200179e71af42ce6e1b91f502e50f915b3)
16 ---
17 src/intel/compiler/brw_fs_generator.cpp | 1 +
18 src/mesa/drivers/dri/i965/intel_extensions.c | 25 +++++++++++++++++++-
19 2 files changed, 25 insertions(+), 1 deletion(-)
20
21 diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
22 index fb77ece30ca..09382775f3e 100644
23 --- a/src/intel/compiler/brw_fs_generator.cpp
24 +++ b/src/intel/compiler/brw_fs_generator.cpp
25 @@ -2100,6 +2100,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
26 break;
27
28 case SHADER_OPCODE_INTERLOCK:
29 + assert(devinfo->gen >= 9);
30 /* The interlock is basically a memory fence issued via sendc */
31 brw_memory_fence(p, dst, BRW_OPCODE_SENDC);
32 break;
33 diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c
34 index a9730ba66fe..92ecd612006 100644
35 --- a/src/mesa/drivers/dri/i965/intel_extensions.c
36 +++ b/src/mesa/drivers/dri/i965/intel_extensions.c
37 @@ -253,7 +253,6 @@ intelInitExtensions(struct gl_context *ctx)
38 ctx->Extensions.EXT_shader_samples_identical = true;
39 ctx->Extensions.OES_primitive_bounding_box = true;
40 ctx->Extensions.OES_texture_buffer = true;
41 - ctx->Extensions.ARB_fragment_shader_interlock = true;
42
43 if (can_do_pipelined_register_writes(brw->screen)) {
44 ctx->Extensions.ARB_draw_indirect = true;
45 @@ -318,6 +317,30 @@ intelInitExtensions(struct gl_context *ctx)
46 ctx->Extensions.KHR_blend_equation_advanced_coherent = true;
47 ctx->Extensions.KHR_texture_compression_astc_ldr = true;
48 ctx->Extensions.KHR_texture_compression_astc_sliced_3d = true;
49 +
50 + /*
51 + * From the Skylake PRM Vol. 7 (Memory Fence Message, page 221):
52 + * "A memory fence message issued by a thread causes further messages
53 + * issued by the thread to be blocked until all previous data port
54 + * messages have completed, or the results can be globally observed from
55 + * the point of view of other threads in the system."
56 + *
57 + * From the Haswell PRM Vol. 7 (Memory Fence, page 256):
58 + * "A memory fence message issued by a thread causes further messages
59 + * issued by the thread to be blocked until all previous messages issued
60 + * by the thread to that data port (data cache or render cache) have
61 + * been globally observed from the point of view of other threads in the
62 + * system."
63 + *
64 + * Summarized: For ARB_fragment_shader_interlock to work, we need to
65 + * ensure memory access ordering for all messages to the dataport from
66 + * all threads. Memory fence messages prior to SKL only provide memory
67 + * access ordering for messages from the same thread, so we can only
68 + * support the feature from Gen9 onwards.
69 + *
70 + */
71 +
72 + ctx->Extensions.ARB_fragment_shader_interlock = true;
73 }
74
75 if (gen_device_info_is_9lp(devinfo))
76 --
77 2.21.0
78

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