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From 42f3bdc5dd962a5958bc024c1e1444248a6b8b4a Mon Sep 17 00:00:00 2001 |
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From: Peter Zijlstra <peterz@infradead.org> |
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Date: Thu, 4 Jan 2018 18:07:12 +0100 |
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Subject: x86/events/intel/ds: Use the proper cache flush method for mapping ds buffers |
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|
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From: Peter Zijlstra <peterz@infradead.org> |
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|
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commit 42f3bdc5dd962a5958bc024c1e1444248a6b8b4a upstream. |
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|
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Thomas reported the following warning: |
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|
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BUG: using smp_processor_id() in preemptible [00000000] code: ovsdb-server/4498 |
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caller is native_flush_tlb_single+0x57/0xc0 |
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native_flush_tlb_single+0x57/0xc0 |
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__set_pte_vaddr+0x2d/0x40 |
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set_pte_vaddr+0x2f/0x40 |
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cea_set_pte+0x30/0x40 |
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ds_update_cea.constprop.4+0x4d/0x70 |
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reserve_ds_buffers+0x159/0x410 |
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x86_reserve_hardware+0x150/0x160 |
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x86_pmu_event_init+0x3e/0x1f0 |
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perf_try_init_event+0x69/0x80 |
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perf_event_alloc+0x652/0x740 |
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SyS_perf_event_open+0x3f6/0xd60 |
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do_syscall_64+0x5c/0x190 |
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|
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set_pte_vaddr is used to map the ds buffers into the cpu entry area, but |
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there are two problems with that: |
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|
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1) The resulting flush is not supposed to be called in preemptible context |
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2) The cpu entry area is supposed to be per CPU, but the debug store |
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buffers are mapped for all CPUs so these mappings need to be flushed |
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globally. |
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|
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Add the necessary preemption protection across the mapping code and flush |
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TLBs globally. |
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|
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Fixes: c1961a4631da ("x86/events/intel/ds: Map debug buffers in cpu_entry_area") |
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Reported-by: Thomas Zeitlhofer <thomas.zeitlhofer+lkml@ze-it.at> |
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Signed-off-by: Peter Zijlstra <peterz@infradead.org> |
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de> |
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Tested-by: Thomas Zeitlhofer <thomas.zeitlhofer+lkml@ze-it.at> |
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Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
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Cc: Hugh Dickins <hughd@google.com> |
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Link: https://lkml.kernel.org/r/20180104170712.GB3040@hirez.programming.kicks-ass.net |
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Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
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|
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--- |
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arch/x86/events/intel/ds.c | 16 ++++++++++++++++ |
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1 file changed, 16 insertions(+) |
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|
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--- a/arch/x86/events/intel/ds.c |
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+++ b/arch/x86/events/intel/ds.c |
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@@ -5,6 +5,7 @@ |
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|
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#include <asm/cpu_entry_area.h> |
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#include <asm/perf_event.h> |
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+#include <asm/tlbflush.h> |
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#include <asm/insn.h> |
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|
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#include "../perf_event.h" |
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@@ -283,20 +284,35 @@ static DEFINE_PER_CPU(void *, insn_buffe |
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static void ds_update_cea(void *cea, void *addr, size_t size, pgprot_t prot) |
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{ |
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+ unsigned long start = (unsigned long)cea; |
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phys_addr_t pa; |
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size_t msz = 0; |
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|
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pa = virt_to_phys(addr); |
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+ |
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+ preempt_disable(); |
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for (; msz < size; msz += PAGE_SIZE, pa += PAGE_SIZE, cea += PAGE_SIZE) |
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cea_set_pte(cea, pa, prot); |
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+ |
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+ /* |
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+ * This is a cross-CPU update of the cpu_entry_area, we must shoot down |
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+ * all TLB entries for it. |
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+ */ |
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+ flush_tlb_kernel_range(start, start + size); |
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+ preempt_enable(); |
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} |
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|
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static void ds_clear_cea(void *cea, size_t size) |
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{ |
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+ unsigned long start = (unsigned long)cea; |
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size_t msz = 0; |
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|
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+ preempt_disable(); |
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for (; msz < size; msz += PAGE_SIZE, cea += PAGE_SIZE) |
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cea_set_pte(cea, 0, PAGE_NONE); |
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+ |
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+ flush_tlb_kernel_range(start, start + size); |
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+ preempt_enable(); |
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} |
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|
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static void *dsalloc_pages(size_t size, gfp_t flags, int cpu) |
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