/[packages]/updates/8/kernel/current/SOURCES/bus-mhi-host-fix-race-between-channel-preparation-an.patch
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Contents of /updates/8/kernel/current/SOURCES/bus-mhi-host-fix-race-between-channel-preparation-an.patch

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Revision 1932936 - (show annotations) (download)
Sat Jan 14 14:55:45 2023 UTC (15 months, 1 week ago) by tmb
File size: 1839 byte(s)
add current -stable queue
1 From f205565c00e0f98575316526fee320307ab0460e Mon Sep 17 00:00:00 2001
2 From: Sasha Levin <sashal@kernel.org>
3 Date: Sun, 16 Oct 2022 11:05:32 +0800
4 Subject: bus: mhi: host: Fix race between channel preparation and M0 event
5
6 From: Qiang Yu <quic_qianyu@quicinc.com>
7
8 [ Upstream commit 869a99907faea6d1835b0bd0d0422ae3519c6ea9 ]
9
10 There is a race condition where mhi_prepare_channel() updates the
11 read and write pointers as the base address and in parallel, if
12 an M0 transition occurs, the tasklet goes ahead and rings
13 doorbells for all channels with a delta in TRE rings assuming
14 they are already enabled. This causes a null pointer access. Fix
15 it by adding a channel enabled check before ringing channel
16 doorbells.
17
18 Cc: stable@vger.kernel.org # 5.19
19 Fixes: a6e2e3522f29 "bus: mhi: core: Add support for PM state transitions"
20 Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
21 Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
22 Link: https://lore.kernel.org/r/1665889532-13634-1-git-send-email-quic_qianyu@quicinc.com
23 [mani: CCed stable list]
24 Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
25 Signed-off-by: Sasha Levin <sashal@kernel.org>
26 ---
27 drivers/bus/mhi/core/pm.c | 3 ++-
28 1 file changed, 2 insertions(+), 1 deletion(-)
29
30 diff --git a/drivers/bus/mhi/core/pm.c b/drivers/bus/mhi/core/pm.c
31 index 1020268a075a..1a87b9c6c2f8 100644
32 --- a/drivers/bus/mhi/core/pm.c
33 +++ b/drivers/bus/mhi/core/pm.c
34 @@ -297,7 +297,8 @@ int mhi_pm_m0_transition(struct mhi_controller *mhi_cntrl)
35 read_lock_irq(&mhi_chan->lock);
36
37 /* Only ring DB if ring is not empty */
38 - if (tre_ring->base && tre_ring->wp != tre_ring->rp)
39 + if (tre_ring->base && tre_ring->wp != tre_ring->rp &&
40 + mhi_chan->ch_state == MHI_CH_STATE_ENABLED)
41 mhi_ring_chan_db(mhi_cntrl, mhi_chan);
42 read_unlock_irq(&mhi_chan->lock);
43 }
44 --
45 2.35.1
46

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