/[packages]/backports/8/kernel/current/SOURCES/net-wireless-rtw89-add-debug-files.patch
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Contents of /backports/8/kernel/current/SOURCES/net-wireless-rtw89-add-debug-files.patch

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Revision 1751299 - (show annotations) (download)
Wed Oct 13 18:02:55 2021 UTC (2 years, 6 months ago) by tmb
File size: 78008 byte(s) 
- update to 5.14.12
  * drop merged/obsolete patches
- add current -stable queue
- fs/ntfs3: Fix integer overflow in ni_fiemap with fiemap_prep()
- fs/ntfs3: Remove unnecessary condition checking from ntfs_file_read_iter
- fs/ntfs3: Remove GPL boilerplates from decompress lib files
- fs/ntfs3: Change how module init/info messages are displayed
- kvm: fix null pointer dereference in page_is_secretmem()
- staging: replace old rtl8188eu with new r8188eu wifi driver from upcoming 5.15
- update rtw89 patchset to v7
1 From f740511370fe4181752b3771e2bd4f671fe3f181 Mon Sep 17 00:00:00 2001
2 From: Ping-Ke Shih <pkshih@realtek.com>
3 Date: Fri, 8 Oct 2021 11:56:07 +0800
4 Subject: [PATCH 04/24] rtw89: add debug files
5
6 To recognize issues happened in field, two debug methods, debug message and
7 debugfs, are added.
8
9 The debug messages are written to kernel log, and four levels can be chosen
10 according to the cases -- debug, info, warn and err.
11
12 Debugfs is used to read and write registers and driver status.
13
14 Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
15 Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
16 Link: https://lore.kernel.org/r/20211008035627.19463-5-pkshih@realtek.com
17 ---
18 drivers/net/wireless/realtek/rtw89/debug.c | 2489 ++++++++++++++++++++
19 drivers/net/wireless/realtek/rtw89/debug.h | 77 +
20 2 files changed, 2566 insertions(+)
21 create mode 100644 drivers/net/wireless/realtek/rtw89/debug.c
22 create mode 100644 drivers/net/wireless/realtek/rtw89/debug.h
23
24 diff --git a/drivers/net/wireless/realtek/rtw89/debug.c b/drivers/net/wireless/realtek/rtw89/debug.c
25 new file mode 100644
26 index 000000000000..29eb188c888c
27 --- /dev/null
28 +++ b/drivers/net/wireless/realtek/rtw89/debug.c
29 @@ -0,0 +1,2489 @@
30 +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
31 +/* Copyright(c) 2019-2020 Realtek Corporation
32 + */
33 +
34 +#include "coex.h"
35 +#include "debug.h"
36 +#include "fw.h"
37 +#include "mac.h"
38 +#include "ps.h"
39 +#include "reg.h"
40 +#include "sar.h"
41 +
42 +#ifdef CONFIG_RTW89_DEBUGMSG
43 +unsigned int rtw89_debug_mask;
44 +EXPORT_SYMBOL(rtw89_debug_mask);
45 +module_param_named(debug_mask, rtw89_debug_mask, uint, 0644);
46 +MODULE_PARM_DESC(debug_mask, "Debugging mask");
47 +#endif
48 +
49 +#ifdef CONFIG_RTW89_DEBUGFS
50 +struct rtw89_debugfs_priv {
51 + struct rtw89_dev *rtwdev;
52 + int (*cb_read)(struct seq_file *m, void *v);
53 + ssize_t (*cb_write)(struct file *filp, const char __user *buffer,
54 + size_t count, loff_t *loff);
55 + union {
56 + u32 cb_data;
57 + struct {
58 + u32 addr;
59 + u8 len;
60 + } read_reg;
61 + struct {
62 + u32 addr;
63 + u32 mask;
64 + u8 path;
65 + } read_rf;
66 + struct {
67 + u8 ss_dbg:1;
68 + u8 dle_dbg:1;
69 + u8 dmac_dbg:1;
70 + u8 cmac_dbg:1;
71 + u8 dbg_port:1;
72 + } dbgpkg_en;
73 + struct {
74 + u32 start;
75 + u32 len;
76 + u8 sel;
77 + } mac_mem;
78 + };
79 +};
80 +
81 +static int rtw89_debugfs_single_show(struct seq_file *m, void *v)
82 +{
83 + struct rtw89_debugfs_priv *debugfs_priv = m->private;
84 +
85 + return debugfs_priv->cb_read(m, v);
86 +}
87 +
88 +static ssize_t rtw89_debugfs_single_write(struct file *filp,
89 + const char __user *buffer,
90 + size_t count, loff_t *loff)
91 +{
92 + struct rtw89_debugfs_priv *debugfs_priv = filp->private_data;
93 +
94 + return debugfs_priv->cb_write(filp, buffer, count, loff);
95 +}
96 +
97 +static ssize_t rtw89_debugfs_seq_file_write(struct file *filp,
98 + const char __user *buffer,
99 + size_t count, loff_t *loff)
100 +{
101 + struct seq_file *seqpriv = (struct seq_file *)filp->private_data;
102 + struct rtw89_debugfs_priv *debugfs_priv = seqpriv->private;
103 +
104 + return debugfs_priv->cb_write(filp, buffer, count, loff);
105 +}
106 +
107 +static int rtw89_debugfs_single_open(struct inode *inode, struct file *filp)
108 +{
109 + return single_open(filp, rtw89_debugfs_single_show, inode->i_private);
110 +}
111 +
112 +static int rtw89_debugfs_close(struct inode *inode, struct file *filp)
113 +{
114 + return 0;
115 +}
116 +
117 +static const struct file_operations file_ops_single_r = {
118 + .owner = THIS_MODULE,
119 + .open = rtw89_debugfs_single_open,
120 + .read = seq_read,
121 + .llseek = seq_lseek,
122 + .release = single_release,
123 +};
124 +
125 +static const struct file_operations file_ops_common_rw = {
126 + .owner = THIS_MODULE,
127 + .open = rtw89_debugfs_single_open,
128 + .release = single_release,
129 + .read = seq_read,
130 + .llseek = seq_lseek,
131 + .write = rtw89_debugfs_seq_file_write,
132 +};
133 +
134 +static const struct file_operations file_ops_single_w = {
135 + .owner = THIS_MODULE,
136 + .write = rtw89_debugfs_single_write,
137 + .open = simple_open,
138 + .release = rtw89_debugfs_close,
139 +};
140 +
141 +static ssize_t
142 +rtw89_debug_priv_read_reg_select(struct file *filp,
143 + const char __user *user_buf,
144 + size_t count, loff_t *loff)
145 +{
146 + struct seq_file *m = (struct seq_file *)filp->private_data;
147 + struct rtw89_debugfs_priv *debugfs_priv = m->private;
148 + struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
149 + char buf[32];
150 + size_t buf_size;
151 + u32 addr, len;
152 + int num;
153 +
154 + buf_size = min(count, sizeof(buf) - 1);
155 + if (copy_from_user(buf, user_buf, buf_size))
156 + return -EFAULT;
157 +
158 + buf[buf_size] = '\0';
159 + num = sscanf(buf, "%x %x", &addr, &len);
160 + if (num != 2) {
161 + rtw89_info(rtwdev, "invalid format: <addr> <len>\n");
162 + return -EINVAL;
163 + }
164 +
165 + debugfs_priv->read_reg.addr = addr;
166 + debugfs_priv->read_reg.len = len;
167 +
168 + rtw89_info(rtwdev, "select read %d bytes from 0x%08x\n", len, addr);
169 +
170 + return count;
171 +}
172 +
173 +static int rtw89_debug_priv_read_reg_get(struct seq_file *m, void *v)
174 +{
175 + struct rtw89_debugfs_priv *debugfs_priv = m->private;
176 + struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
177 + u32 addr, data;
178 + u8 len;
179 +
180 + len = debugfs_priv->read_reg.len;
181 + addr = debugfs_priv->read_reg.addr;
182 +
183 + switch (len) {
184 + case 1:
185 + data = rtw89_read8(rtwdev, addr);
186 + break;
187 + case 2:
188 + data = rtw89_read16(rtwdev, addr);
189 + break;
190 + case 4:
191 + data = rtw89_read32(rtwdev, addr);
192 + break;
193 + default:
194 + rtw89_info(rtwdev, "invalid read reg len %d\n", len);
195 + return -EINVAL;
196 + }
197 +
198 + seq_printf(m, "get %d bytes at 0x%08x=0x%08x\n", len, addr, data);
199 +
200 + return 0;
201 +}
202 +
203 +static ssize_t rtw89_debug_priv_write_reg_set(struct file *filp,
204 + const char __user *user_buf,
205 + size_t count, loff_t *loff)
206 +{
207 + struct rtw89_debugfs_priv *debugfs_priv = filp->private_data;
208 + struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
209 + char buf[32];
210 + size_t buf_size;
211 + u32 addr, val, len;
212 + int num;
213 +
214 + buf_size = min(count, sizeof(buf) - 1);
215 + if (copy_from_user(buf, user_buf, buf_size))
216 + return -EFAULT;
217 +
218 + buf[buf_size] = '\0';
219 + num = sscanf(buf, "%x %x %x", &addr, &val, &len);
220 + if (num != 3) {
221 + rtw89_info(rtwdev, "invalid format: <addr> <val> <len>\n");
222 + return -EINVAL;
223 + }
224 +
225 + switch (len) {
226 + case 1:
227 + rtw89_info(rtwdev, "reg write8 0x%08x: 0x%02x\n", addr, val);
228 + rtw89_write8(rtwdev, addr, (u8)val);
229 + break;
230 + case 2:
231 + rtw89_info(rtwdev, "reg write16 0x%08x: 0x%04x\n", addr, val);
232 + rtw89_write16(rtwdev, addr, (u16)val);
233 + break;
234 + case 4:
235 + rtw89_info(rtwdev, "reg write32 0x%08x: 0x%08x\n", addr, val);
236 + rtw89_write32(rtwdev, addr, (u32)val);
237 + break;
238 + default:
239 + rtw89_info(rtwdev, "invalid read write len %d\n", len);
240 + break;
241 + }
242 +
243 + return count;
244 +}
245 +
246 +static ssize_t
247 +rtw89_debug_priv_read_rf_select(struct file *filp,
248 + const char __user *user_buf,
249 + size_t count, loff_t *loff)
250 +{
251 + struct seq_file *m = (struct seq_file *)filp->private_data;
252 + struct rtw89_debugfs_priv *debugfs_priv = m->private;
253 + struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
254 + char buf[32];
255 + size_t buf_size;
256 + u32 addr, mask;
257 + u8 path;
258 + int num;
259 +
260 + buf_size = min(count, sizeof(buf) - 1);
261 + if (copy_from_user(buf, user_buf, buf_size))
262 + return -EFAULT;
263 +
264 + buf[buf_size] = '\0';
265 + num = sscanf(buf, "%hhd %x %x", &path, &addr, &mask);
266 + if (num != 3) {
267 + rtw89_info(rtwdev, "invalid format: <path> <addr> <mask>\n");
268 + return -EINVAL;
269 + }
270 +
271 + if (path >= rtwdev->chip->rf_path_num) {
272 + rtw89_info(rtwdev, "wrong rf path\n");
273 + return -EINVAL;
274 + }
275 + debugfs_priv->read_rf.addr = addr;
276 + debugfs_priv->read_rf.mask = mask;
277 + debugfs_priv->read_rf.path = path;
278 +
279 + rtw89_info(rtwdev, "select read rf path %d from 0x%08x\n", path, addr);
280 +
281 + return count;
282 +}
283 +
284 +static int rtw89_debug_priv_read_rf_get(struct seq_file *m, void *v)
285 +{
286 + struct rtw89_debugfs_priv *debugfs_priv = m->private;
287 + struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
288 + u32 addr, data, mask;
289 + u8 path;
290 +
291 + addr = debugfs_priv->read_rf.addr;
292 + mask = debugfs_priv->read_rf.mask;
293 + path = debugfs_priv->read_rf.path;
294 +
295 + data = rtw89_read_rf(rtwdev, path, addr, mask);
296 +
297 + seq_printf(m, "path %d, rf register 0x%08x=0x%08x\n", path, addr, data);
298 +
299 + return 0;
300 +}
301 +
302 +static ssize_t rtw89_debug_priv_write_rf_set(struct file *filp,
303 + const char __user *user_buf,
304 + size_t count, loff_t *loff)
305 +{
306 + struct rtw89_debugfs_priv *debugfs_priv = filp->private_data;
307 + struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
308 + char buf[32];
309 + size_t buf_size;
310 + u32 addr, val, mask;
311 + u8 path;
312 + int num;
313 +
314 + buf_size = min(count, sizeof(buf) - 1);
315 + if (copy_from_user(buf, user_buf, buf_size))
316 + return -EFAULT;
317 +
318 + buf[buf_size] = '\0';
319 + num = sscanf(buf, "%hhd %x %x %x", &path, &addr, &mask, &val);
320 + if (num != 4) {
321 + rtw89_info(rtwdev, "invalid format: <path> <addr> <mask> <val>\n");
322 + return -EINVAL;
323 + }
324 +
325 + if (path >= rtwdev->chip->rf_path_num) {
326 + rtw89_info(rtwdev, "wrong rf path\n");
327 + return -EINVAL;
328 + }
329 +
330 + rtw89_info(rtwdev, "path %d, rf register write 0x%08x=0x%08x (mask = 0x%08x)\n",
331 + path, addr, val, mask);
332 + rtw89_write_rf(rtwdev, path, addr, mask, val);
333 +
334 + return count;
335 +}
336 +
337 +static int rtw89_debug_priv_rf_reg_dump_get(struct seq_file *m, void *v)
338 +{
339 + struct rtw89_debugfs_priv *debugfs_priv = m->private;
340 + struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
341 + const struct rtw89_chip_info *chip = rtwdev->chip;
342 + u32 addr, offset, data;
343 + u8 path;
344 +
345 + for (path = 0; path < chip->rf_path_num; path++) {
346 + seq_printf(m, "RF path %d:\n\n", path);
347 + for (addr = 0; addr < 0x100; addr += 4) {
348 + seq_printf(m, "0x%08x: ", addr);
349 + for (offset = 0; offset < 4; offset++) {
350 + data = rtw89_read_rf(rtwdev, path,
351 + addr + offset, RFREG_MASK);
352 + seq_printf(m, "0x%05x ", data);
353 + }
354 + seq_puts(m, "\n");
355 + }
356 + seq_puts(m, "\n");
357 + }
358 +
359 + return 0;
360 +}
361 +
362 +struct txpwr_ent {
363 + const char *txt;
364 + u8 len;
365 +};
366 +
367 +struct txpwr_map {
368 + const struct txpwr_ent *ent;
369 + u8 size;
370 + u32 addr_from;
371 + u32 addr_to;
372 +};
373 +
374 +#define __GEN_TXPWR_ENT2(_t, _e0, _e1) \
375 + { .len = 2, .txt = _t "\t- " _e0 " " _e1 }
376 +
377 +#define __GEN_TXPWR_ENT4(_t, _e0, _e1, _e2, _e3) \
378 + { .len = 4, .txt = _t "\t- " _e0 " " _e1 " " _e2 " " _e3 }
379 +
380 +#define __GEN_TXPWR_ENT8(_t, _e0, _e1, _e2, _e3, _e4, _e5, _e6, _e7) \
381 + { .len = 8, .txt = _t "\t- " \
382 + _e0 " " _e1 " " _e2 " " _e3 " " \
383 + _e4 " " _e5 " " _e6 " " _e7 }
384 +
385 +static const struct txpwr_ent __txpwr_ent_byr[] = {
386 + __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "),
387 + __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "),
388 + __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "),
389 + /* 1NSS */
390 + __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "),
391 + __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "),
392 + __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"),
393 + __GEN_TXPWR_ENT4("HEDCM_1NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "),
394 + /* 2NSS */
395 + __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "),
396 + __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "),
397 + __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"),
398 + __GEN_TXPWR_ENT4("HEDCM_2NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "),
399 +};
400 +
401 +static_assert((ARRAY_SIZE(__txpwr_ent_byr) * 4) ==
402 + (R_AX_PWR_BY_RATE_MAX - R_AX_PWR_BY_RATE + 4));
403 +
404 +static const struct txpwr_map __txpwr_map_byr = {
405 + .ent = __txpwr_ent_byr,
406 + .size = ARRAY_SIZE(__txpwr_ent_byr),
407 + .addr_from = R_AX_PWR_BY_RATE,
408 + .addr_to = R_AX_PWR_BY_RATE_MAX,
409 +};
410 +
411 +static const struct txpwr_ent __txpwr_ent_lmt[] = {
412 + /* 1TX */
413 + __GEN_TXPWR_ENT2("CCK_1TX_20M ", "NON_BF", "BF"),
414 + __GEN_TXPWR_ENT2("CCK_1TX_40M ", "NON_BF", "BF"),
415 + __GEN_TXPWR_ENT2("OFDM_1TX ", "NON_BF", "BF"),
416 + __GEN_TXPWR_ENT2("MCS_1TX_20M_0 ", "NON_BF", "BF"),
417 + __GEN_TXPWR_ENT2("MCS_1TX_20M_1 ", "NON_BF", "BF"),
418 + __GEN_TXPWR_ENT2("MCS_1TX_20M_2 ", "NON_BF", "BF"),
419 + __GEN_TXPWR_ENT2("MCS_1TX_20M_3 ", "NON_BF", "BF"),
420 + __GEN_TXPWR_ENT2("MCS_1TX_20M_4 ", "NON_BF", "BF"),
421 + __GEN_TXPWR_ENT2("MCS_1TX_20M_5 ", "NON_BF", "BF"),
422 + __GEN_TXPWR_ENT2("MCS_1TX_20M_6 ", "NON_BF", "BF"),
423 + __GEN_TXPWR_ENT2("MCS_1TX_20M_7 ", "NON_BF", "BF"),
424 + __GEN_TXPWR_ENT2("MCS_1TX_40M_0 ", "NON_BF", "BF"),
425 + __GEN_TXPWR_ENT2("MCS_1TX_40M_1 ", "NON_BF", "BF"),
426 + __GEN_TXPWR_ENT2("MCS_1TX_40M_2 ", "NON_BF", "BF"),
427 + __GEN_TXPWR_ENT2("MCS_1TX_40M_3 ", "NON_BF", "BF"),
428 + __GEN_TXPWR_ENT2("MCS_1TX_80M_0 ", "NON_BF", "BF"),
429 + __GEN_TXPWR_ENT2("MCS_1TX_80M_1 ", "NON_BF", "BF"),
430 + __GEN_TXPWR_ENT2("MCS_1TX_160M ", "NON_BF", "BF"),
431 + __GEN_TXPWR_ENT2("MCS_1TX_40M_0p5", "NON_BF", "BF"),
432 + __GEN_TXPWR_ENT2("MCS_1TX_40M_2p5", "NON_BF", "BF"),
433 + /* 2TX */
434 + __GEN_TXPWR_ENT2("CCK_2TX_20M ", "NON_BF", "BF"),
435 + __GEN_TXPWR_ENT2("CCK_2TX_40M ", "NON_BF", "BF"),
436 + __GEN_TXPWR_ENT2("OFDM_2TX ", "NON_BF", "BF"),
437 + __GEN_TXPWR_ENT2("MCS_2TX_20M_0 ", "NON_BF", "BF"),
438 + __GEN_TXPWR_ENT2("MCS_2TX_20M_1 ", "NON_BF", "BF"),
439 + __GEN_TXPWR_ENT2("MCS_2TX_20M_2 ", "NON_BF", "BF"),
440 + __GEN_TXPWR_ENT2("MCS_2TX_20M_3 ", "NON_BF", "BF"),
441 + __GEN_TXPWR_ENT2("MCS_2TX_20M_4 ", "NON_BF", "BF"),
442 + __GEN_TXPWR_ENT2("MCS_2TX_20M_5 ", "NON_BF", "BF"),
443 + __GEN_TXPWR_ENT2("MCS_2TX_20M_6 ", "NON_BF", "BF"),
444 + __GEN_TXPWR_ENT2("MCS_2TX_20M_7 ", "NON_BF", "BF"),
445 + __GEN_TXPWR_ENT2("MCS_2TX_40M_0 ", "NON_BF", "BF"),
446 + __GEN_TXPWR_ENT2("MCS_2TX_40M_1 ", "NON_BF", "BF"),
447 + __GEN_TXPWR_ENT2("MCS_2TX_40M_2 ", "NON_BF", "BF"),
448 + __GEN_TXPWR_ENT2("MCS_2TX_40M_3 ", "NON_BF", "BF"),
449 + __GEN_TXPWR_ENT2("MCS_2TX_80M_0 ", "NON_BF", "BF"),
450 + __GEN_TXPWR_ENT2("MCS_2TX_80M_1 ", "NON_BF", "BF"),
451 + __GEN_TXPWR_ENT2("MCS_2TX_160M ", "NON_BF", "BF"),
452 + __GEN_TXPWR_ENT2("MCS_2TX_40M_0p5", "NON_BF", "BF"),
453 + __GEN_TXPWR_ENT2("MCS_2TX_40M_2p5", "NON_BF", "BF"),
454 +};
455 +
456 +static_assert((ARRAY_SIZE(__txpwr_ent_lmt) * 2) ==
457 + (R_AX_PWR_LMT_MAX - R_AX_PWR_LMT + 4));
458 +
459 +static const struct txpwr_map __txpwr_map_lmt = {
460 + .ent = __txpwr_ent_lmt,
461 + .size = ARRAY_SIZE(__txpwr_ent_lmt),
462 + .addr_from = R_AX_PWR_LMT,
463 + .addr_to = R_AX_PWR_LMT_MAX,
464 +};
465 +
466 +static const struct txpwr_ent __txpwr_ent_lmt_ru[] = {
467 + /* 1TX */
468 + __GEN_TXPWR_ENT8("1TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3",
469 + "RU26__4", "RU26__5", "RU26__6", "RU26__7"),
470 + __GEN_TXPWR_ENT8("1TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3",
471 + "RU52__4", "RU52__5", "RU52__6", "RU52__7"),
472 + __GEN_TXPWR_ENT8("1TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3",
473 + "RU106_4", "RU106_5", "RU106_6", "RU106_7"),
474 + /* 2TX */
475 + __GEN_TXPWR_ENT8("2TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3",
476 + "RU26__4", "RU26__5", "RU26__6", "RU26__7"),
477 + __GEN_TXPWR_ENT8("2TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3",
478 + "RU52__4", "RU52__5", "RU52__6", "RU52__7"),
479 + __GEN_TXPWR_ENT8("2TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3",
480 + "RU106_4", "RU106_5", "RU106_6", "RU106_7"),
481 +};
482 +
483 +static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru) * 8) ==
484 + (R_AX_PWR_RU_LMT_MAX - R_AX_PWR_RU_LMT + 4));
485 +
486 +static const struct txpwr_map __txpwr_map_lmt_ru = {
487 + .ent = __txpwr_ent_lmt_ru,
488 + .size = ARRAY_SIZE(__txpwr_ent_lmt_ru),
489 + .addr_from = R_AX_PWR_RU_LMT,
490 + .addr_to = R_AX_PWR_RU_LMT_MAX,
491 +};
492 +
493 +static u8 __print_txpwr_ent(struct seq_file *m, const struct txpwr_ent *ent,
494 + const u8 *buf, const u8 cur)
495 +{
496 + char *fmt;
497 +
498 + switch (ent->len) {
499 + case 2:
500 + fmt = "%s\t| %3d, %3d,\tdBm\n";
501 + seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1]);
502 + return 2;
503 + case 4:
504 + fmt = "%s\t| %3d, %3d, %3d, %3d,\tdBm\n";
505 + seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1],
506 + buf[cur + 2], buf[cur + 3]);
507 + return 4;
508 + case 8:
509 + fmt = "%s\t| %3d, %3d, %3d, %3d, %3d, %3d, %3d, %3d,\tdBm\n";
510 + seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1],
511 + buf[cur + 2], buf[cur + 3], buf[cur + 4],
512 + buf[cur + 5], buf[cur + 6], buf[cur + 7]);
513 + return 8;
514 + default:
515 + return 0;
516 + }
517 +}
518 +
519 +static int __print_txpwr_map(struct seq_file *m, struct rtw89_dev *rtwdev,
520 + const struct txpwr_map *map)
521 +{
522 + u8 fct = rtwdev->chip->txpwr_factor_mac;
523 + u8 *buf, cur, i;
524 + u32 val, addr;
525 + int ret;
526 +
527 + buf = vzalloc(map->addr_to - map->addr_from + 4);
528 + if (!buf)
529 + return -ENOMEM;
530 +
531 + for (addr = map->addr_from; addr <= map->addr_to; addr += 4) {
532 + ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val);
533 + if (ret)
534 + val = MASKDWORD;
535 +
536 + cur = addr - map->addr_from;
537 + for (i = 0; i < 4; i++, val >>= 8)
538 + buf[cur + i] = FIELD_GET(MASKBYTE0, val) >> fct;
539 + }
540 +
541 + for (cur = 0, i = 0; i < map->size; i++)
542 + cur += __print_txpwr_ent(m, &map->ent[i], buf, cur);
543 +
544 + vfree(buf);
545 + return 0;
546 +}
547 +
548 +#define case_REGD(_regd) \
549 + case RTW89_ ## _regd: \
550 + seq_puts(m, #_regd "\n"); \
551 + break
552 +
553 +static void __print_regd(struct seq_file *m, struct rtw89_dev *rtwdev)
554 +{
555 + u8 band = rtwdev->hal.current_band_type;
556 + u8 regd = rtw89_regd_get(rtwdev, band);
557 +
558 + switch (regd) {
559 + default:
560 + seq_printf(m, "UNKNOWN: %d\n", regd);
561 + break;
562 + case_REGD(WW);
563 + case_REGD(ETSI);
564 + case_REGD(FCC);
565 + case_REGD(MKK);
566 + case_REGD(NA);
567 + case_REGD(IC);
568 + case_REGD(KCC);
569 + case_REGD(NCC);
570 + case_REGD(CHILE);
571 + case_REGD(ACMA);
572 + case_REGD(MEXICO);
573 + case_REGD(UKRAINE);
574 + case_REGD(CN);
575 + }
576 +}
577 +
578 +#undef case_REGD
579 +
580 +static int rtw89_debug_priv_txpwr_table_get(struct seq_file *m, void *v)
581 +{
582 + struct rtw89_debugfs_priv *debugfs_priv = m->private;
583 + struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
584 + int ret = 0;
585 +
586 + mutex_lock(&rtwdev->mutex);
587 + rtw89_leave_ps_mode(rtwdev);
588 +
589 + seq_puts(m, "[Regulatory] ");
590 + __print_regd(m, rtwdev);
591 +
592 + seq_puts(m, "[SAR]\n");
593 + rtw89_print_sar(m, rtwdev);
594 +
595 + seq_puts(m, "\n[TX power byrate]\n");
596 + ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_byr);
597 + if (ret)
598 + goto err;
599 +
600 + seq_puts(m, "\n[TX power limit]\n");
601 + ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt);
602 + if (ret)
603 + goto err;
604 +
605 + seq_puts(m, "\n[TX power limit_ru]\n");
606 + ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt_ru);
607 + if (ret)
608 + goto err;
609 +
610 +err:
611 + mutex_unlock(&rtwdev->mutex);
612 + return ret;
613 +}
614 +
615 +static ssize_t
616 +rtw89_debug_priv_mac_reg_dump_select(struct file *filp,
617 + const char __user *user_buf,
618 + size_t count, loff_t *loff)
619 +{
620 + struct seq_file *m = (struct seq_file *)filp->private_data;
621 + struct rtw89_debugfs_priv *debugfs_priv = m->private;
622 + struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
623 + char buf[32];
624 + size_t buf_size;
625 + int sel;
626 + int ret;
627 +
628 + buf_size = min(count, sizeof(buf) - 1);
629 + if (copy_from_user(buf, user_buf, buf_size))
630 + return -EFAULT;
631 +
632 + buf[buf_size] = '\0';
633 + ret = kstrtoint(buf, 0, &sel);
634 + if (ret)
635 + return ret;
636 +
637 + if (sel < RTW89_DBG_SEL_MAC_00 || sel > RTW89_DBG_SEL_RFC) {
638 + rtw89_info(rtwdev, "invalid args: %d\n", sel);
639 + return -EINVAL;
640 + }
641 +
642 + debugfs_priv->cb_data = sel;
643 + rtw89_info(rtwdev, "select mac page dump %d\n", debugfs_priv->cb_data);
644 +
645 + return count;
646 +}
647 +
648 +#define RTW89_MAC_PAGE_SIZE 0x100
649 +
650 +static int rtw89_debug_priv_mac_reg_dump_get(struct seq_file *m, void *v)
651 +{
652 + struct rtw89_debugfs_priv *debugfs_priv = m->private;
653 + struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
654 + enum rtw89_debug_mac_reg_sel reg_sel = debugfs_priv->cb_data;
655 + u32 start, end;
656 + u32 i, j, k, page;
657 + u32 val;
658 +
659 + switch (reg_sel) {
660 + case RTW89_DBG_SEL_MAC_00:
661 + seq_puts(m, "Debug selected MAC page 0x00\n");
662 + start = 0x000;
663 + end = 0x014;
664 + break;
665 + case RTW89_DBG_SEL_MAC_40:
666 + seq_puts(m, "Debug selected MAC page 0x40\n");
667 + start = 0x040;
668 + end = 0x07f;
669 + break;
670 + case RTW89_DBG_SEL_MAC_80:
671 + seq_puts(m, "Debug selected MAC page 0x80\n");
672 + start = 0x080;
673 + end = 0x09f;
674 + break;
675 + case RTW89_DBG_SEL_MAC_C0:
676 + seq_puts(m, "Debug selected MAC page 0xc0\n");
677 + start = 0x0c0;
678 + end = 0x0df;
679 + break;
680 + case RTW89_DBG_SEL_MAC_E0:
681 + seq_puts(m, "Debug selected MAC page 0xe0\n");
682 + start = 0x0e0;
683 + end = 0x0ff;
684 + break;
685 + case RTW89_DBG_SEL_BB:
686 + seq_puts(m, "Debug selected BB register\n");
687 + start = 0x100;
688 + end = 0x17f;
689 + break;
690 + case RTW89_DBG_SEL_IQK:
691 + seq_puts(m, "Debug selected IQK register\n");
692 + start = 0x180;
693 + end = 0x1bf;
694 + break;
695 + case RTW89_DBG_SEL_RFC:
696 + seq_puts(m, "Debug selected RFC register\n");
697 + start = 0x1c0;
698 + end = 0x1ff;
699 + break;
700 + default:
701 + seq_puts(m, "Selected invalid register page\n");
702 + return -EINVAL;
703 + }
704 +
705 + for (i = start; i <= end; i++) {
706 + page = i << 8;
707 + for (j = page; j < page + RTW89_MAC_PAGE_SIZE; j += 16) {
708 + seq_printf(m, "%08xh : ", 0x18600000 + j);
709 + for (k = 0; k < 4; k++) {
710 + val = rtw89_read32(rtwdev, j + (k << 2));
711 + seq_printf(m, "%08x ", val);
712 + }
713 + seq_puts(m, "\n");
714 + }
715 + }
716 +
717 + return 0;
718 +}
719 +
720 +static ssize_t
721 +rtw89_debug_priv_mac_mem_dump_select(struct file *filp,
722 + const char __user *user_buf,
723 + size_t count, loff_t *loff)
724 +{
725 + struct seq_file *m = (struct seq_file *)filp->private_data;
726 + struct rtw89_debugfs_priv *debugfs_priv = m->private;
727 + struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
728 + char buf[32];
729 + size_t buf_size;
730 + u32 sel, start_addr, len;
731 + int num;
732 +
733 + buf_size = min(count, sizeof(buf) - 1);
734 + if (copy_from_user(buf, user_buf, buf_size))
735 + return -EFAULT;
736 +
737 + buf[buf_size] = '\0';
738 + num = sscanf(buf, "%x %x %x", &sel, &start_addr, &len);
739 + if (num != 3) {
740 + rtw89_info(rtwdev, "invalid format: <sel> <start> <len>\n");
741 + return -EINVAL;
742 + }
743 +
744 + debugfs_priv->mac_mem.sel = sel;
745 + debugfs_priv->mac_mem.start = start_addr;
746 + debugfs_priv->mac_mem.len = len;
747 +
748 + rtw89_info(rtwdev, "select mem %d start %d len %d\n",
749 + sel, start_addr, len);
750 +
751 + return count;
752 +}
753 +
754 +static const u32 mac_mem_base_addr_table[RTW89_MAC_MEM_MAX] = {
755 + [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR,
756 + [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR,
757 + [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR,
758 + [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR,
759 + [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR,
760 + [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR,
761 + [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR,
762 + [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR,
763 + [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR,
764 + [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR,
765 + [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR,
766 + [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR,
767 +};
768 +
769 +static void rtw89_debug_dump_mac_mem(struct seq_file *m,
770 + struct rtw89_dev *rtwdev,
771 + u8 sel, u32 start_addr, u32 len)
772 +{
773 + u32 base_addr, start_page, residue;
774 + u32 i, j, p, pages;
775 + u32 dump_len, remain;
776 + u32 val;
777 +
778 + remain = len;
779 + pages = len / MAC_MEM_DUMP_PAGE_SIZE + 1;
780 + start_page = start_addr / MAC_MEM_DUMP_PAGE_SIZE;
781 + residue = start_addr % MAC_MEM_DUMP_PAGE_SIZE;
782 + base_addr = mac_mem_base_addr_table[sel];
783 + base_addr += start_page * MAC_MEM_DUMP_PAGE_SIZE;
784 +
785 + for (p = 0; p < pages; p++) {
786 + dump_len = min_t(u32, remain, MAC_MEM_DUMP_PAGE_SIZE);
787 + rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, base_addr);
788 + for (i = R_AX_INDIR_ACCESS_ENTRY + residue;
789 + i < R_AX_INDIR_ACCESS_ENTRY + dump_len;) {
790 + seq_printf(m, "%08xh:", i);
791 + for (j = 0;
792 + j < 4 && i < R_AX_INDIR_ACCESS_ENTRY + dump_len;
793 + j++, i += 4) {
794 + val = rtw89_read32(rtwdev, i);
795 + seq_printf(m, " %08x", val);
796 + remain -= 4;
797 + }
798 + seq_puts(m, "\n");
799 + }
800 + base_addr += MAC_MEM_DUMP_PAGE_SIZE;
801 + }
802 +}
803 +
804 +static int
805 +rtw89_debug_priv_mac_mem_dump_get(struct seq_file *m, void *v)
806 +{
807 + struct rtw89_debugfs_priv *debugfs_priv = m->private;
808 + struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
809 +
810 + mutex_lock(&rtwdev->mutex);
811 + rtw89_leave_ps_mode(rtwdev);
812 + rtw89_debug_dump_mac_mem(m, rtwdev,
813 + debugfs_priv->mac_mem.sel,
814 + debugfs_priv->mac_mem.start,
815 + debugfs_priv->mac_mem.len);
816 + mutex_unlock(&rtwdev->mutex);
817 +
818 + return 0;
819 +}
820 +
821 +static ssize_t
822 +rtw89_debug_priv_mac_dbg_port_dump_select(struct file *filp,
823 + const char __user *user_buf,
824 + size_t count, loff_t *loff)
825 +{
826 + struct seq_file *m = (struct seq_file *)filp->private_data;
827 + struct rtw89_debugfs_priv *debugfs_priv = m->private;
828 + struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
829 + char buf[32];
830 + size_t buf_size;
831 + int sel, set;
832 + int num;
833 + bool enable;
834 +
835 + buf_size = min(count, sizeof(buf) - 1);
836 + if (copy_from_user(buf, user_buf, buf_size))
837 + return -EFAULT;
838 +
839 + buf[buf_size] = '\0';
840 + num = sscanf(buf, "%d %d", &sel, &set);
841 + if (num != 2) {
842 + rtw89_info(rtwdev, "invalid format: <sel> <set>\n");
843 + return -EINVAL;
844 + }
845 +
846 + enable = set == 0 ? false : true;
847 + switch (sel) {
848 + case 0:
849 + debugfs_priv->dbgpkg_en.ss_dbg = enable;
850 + break;
851 + case 1:
852 + debugfs_priv->dbgpkg_en.dle_dbg = enable;
853 + break;
854 + case 2:
855 + debugfs_priv->dbgpkg_en.dmac_dbg = enable;
856 + break;
857 + case 3:
858 + debugfs_priv->dbgpkg_en.cmac_dbg = enable;
859 + break;
860 + case 4:
861 + debugfs_priv->dbgpkg_en.dbg_port = enable;
862 + break;
863 + default:
864 + rtw89_info(rtwdev, "invalid args: sel %d set %d\n", sel, set);
865 + return -EINVAL;
866 + }
867 +
868 + rtw89_info(rtwdev, "%s debug port dump %d\n",
869 + enable ? "Enable" : "Disable", sel);
870 +
871 + return count;
872 +}
873 +
874 +static int rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev *rtwdev,
875 + struct seq_file *m)
876 +{
877 + return 0;
878 +}
879 +
880 +static int rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev *rtwdev,
881 + struct seq_file *m)
882 +{
883 +#define DLE_DFI_DUMP(__type, __target, __sel) \
884 +({ \
885 + u32 __ctrl; \
886 + u32 __reg_ctrl = R_AX_##__type##_DBG_FUN_INTF_CTL; \
887 + u32 __reg_data = R_AX_##__type##_DBG_FUN_INTF_DATA; \
888 + u32 __data, __val32; \
889 + int __ret; \
890 + \
891 + __ctrl = FIELD_PREP(B_AX_##__type##_DFI_TRGSEL_MASK, \
892 + DLE_DFI_TYPE_##__target) | \
893 + FIELD_PREP(B_AX_##__type##_DFI_ADDR_MASK, __sel) | \
894 + B_AX_WDE_DFI_ACTIVE; \
895 + rtw89_write32(rtwdev, __reg_ctrl, __ctrl); \
896 + __ret = read_poll_timeout(rtw89_read32, __val32, \
897 + !(__val32 & B_AX_##__type##_DFI_ACTIVE), \
898 + 1000, 50000, false, \
899 + rtwdev, __reg_ctrl); \
900 + if (__ret) { \
901 + rtw89_err(rtwdev, "failed to dump DLE %s %s %d\n", \
902 + #__type, #__target, __sel); \
903 + return __ret; \
904 + } \
905 + \
906 + __data = rtw89_read32(rtwdev, __reg_data); \
907 + __data; \
908 +})
909 +
910 +#define DLE_DFI_FREE_PAGE_DUMP(__m, __type) \
911 +({ \
912 + u32 __freepg, __pubpg; \
913 + u32 __freepg_head, __freepg_tail, __pubpg_num; \
914 + \
915 + __freepg = DLE_DFI_DUMP(__type, FREEPG, 0); \
916 + __pubpg = DLE_DFI_DUMP(__type, FREEPG, 1); \
917 + __freepg_head = FIELD_GET(B_AX_DLE_FREE_HEADPG, __freepg); \
918 + __freepg_tail = FIELD_GET(B_AX_DLE_FREE_TAILPG, __freepg); \
919 + __pubpg_num = FIELD_GET(B_AX_DLE_PUB_PGNUM, __pubpg); \
920 + seq_printf(__m, "[%s] freepg head: %d\n", \
921 + #__type, __freepg_head); \
922 + seq_printf(__m, "[%s] freepg tail: %d\n", \
923 + #__type, __freepg_tail); \
924 + seq_printf(__m, "[%s] pubpg num : %d\n", \
925 + #__type, __pubpg_num); \
926 +})
927 +
928 +#define case_QUOTA(__m, __type, __id) \
929 + case __type##_QTAID_##__id: \
930 + val32 = DLE_DFI_DUMP(__type, QUOTA, __type##_QTAID_##__id); \
931 + rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, val32); \
932 + use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, val32); \
933 + seq_printf(__m, "[%s][%s] rsv_pgnum: %d\n", \
934 + #__type, #__id, rsv_pgnum); \
935 + seq_printf(__m, "[%s][%s] use_pgnum: %d\n", \
936 + #__type, #__id, use_pgnum); \
937 + break
938 + u32 quota_id;
939 + u32 val32;
940 + u16 rsv_pgnum, use_pgnum;
941 + int ret;
942 +
943 + ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL);
944 + if (ret) {
945 + seq_puts(m, "[DLE] : DMAC not enabled\n");
946 + return ret;
947 + }
948 +
949 + DLE_DFI_FREE_PAGE_DUMP(m, WDE);
950 + DLE_DFI_FREE_PAGE_DUMP(m, PLE);
951 + for (quota_id = 0; quota_id <= WDE_QTAID_CPUIO; quota_id++) {
952 + switch (quota_id) {
953 + case_QUOTA(m, WDE, HOST_IF);
954 + case_QUOTA(m, WDE, WLAN_CPU);
955 + case_QUOTA(m, WDE, DATA_CPU);
956 + case_QUOTA(m, WDE, PKTIN);
957 + case_QUOTA(m, WDE, CPUIO);
958 + }
959 + }
960 + for (quota_id = 0; quota_id <= PLE_QTAID_CPUIO; quota_id++) {
961 + switch (quota_id) {
962 + case_QUOTA(m, PLE, B0_TXPL);
963 + case_QUOTA(m, PLE, B1_TXPL);
964 + case_QUOTA(m, PLE, C2H);
965 + case_QUOTA(m, PLE, H2C);
966 + case_QUOTA(m, PLE, WLAN_CPU);
967 + case_QUOTA(m, PLE, MPDU);
968 + case_QUOTA(m, PLE, CMAC0_RX);
969 + case_QUOTA(m, PLE, CMAC1_RX);
970 + case_QUOTA(m, PLE, CMAC1_BBRPT);
971 + case_QUOTA(m, PLE, WDRLS);
972 + case_QUOTA(m, PLE, CPUIO);
973 + }
974 + }
975 +
976 + return 0;
977 +
978 +#undef case_QUOTA
979 +#undef DLE_DFI_DUMP
980 +#undef DLE_DFI_FREE_PAGE_DUMP
981 +}
982 +
983 +static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev,
984 + struct seq_file *m)
985 +{
986 + int ret;
987 +
988 + ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL);
989 + if (ret) {
990 + seq_puts(m, "[DMAC] : DMAC not enabled\n");
991 + return ret;
992 + }
993 +
994 + seq_printf(m, "R_AX_DMAC_ERR_ISR=0x%08x\n",
995 + rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR));
996 + seq_printf(m, "[0]R_AX_WDRLS_ERR_ISR=0x%08x\n",
997 + rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR));
998 + seq_printf(m, "[1]R_AX_SEC_ERR_IMR_ISR=0x%08x\n",
999 + rtw89_read32(rtwdev, R_AX_SEC_ERR_IMR_ISR));
1000 + seq_printf(m, "[2.1]R_AX_MPDU_TX_ERR_ISR=0x%08x\n",
1001 + rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR));
1002 + seq_printf(m, "[2.2]R_AX_MPDU_RX_ERR_ISR=0x%08x\n",
1003 + rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR));
1004 + seq_printf(m, "[3]R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n",
1005 + rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR));
1006 + seq_printf(m, "[4]R_AX_WDE_ERR_ISR=0x%08x\n",
1007 + rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
1008 + seq_printf(m, "[5.1]R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n",
1009 + rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR));
1010 + seq_printf(m, "[5.2]R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n",
1011 + rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1));
1012 + seq_printf(m, "[6]R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
1013 + rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
1014 + seq_printf(m, "[7]R_AX_PKTIN_ERR_ISR=0x%08x\n",
1015 + rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR));
1016 + seq_printf(m, "[8.1]R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n",
1017 + rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR));
1018 + seq_printf(m, "[8.2]R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n",
1019 + rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR));
1020 + seq_printf(m, "[8.3]R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n",
1021 + rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR));
1022 + seq_printf(m, "[10]R_AX_CPUIO_ERR_ISR=0x%08x\n",
1023 + rtw89_read32(rtwdev, R_AX_CPUIO_ERR_ISR));
1024 + seq_printf(m, "[11.1]R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n",
1025 + rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR));
1026 + seq_printf(m, "[11.2]R_AX_BBRPT_CHINFO_ERR_IMR_ISR=0x%08x\n",
1027 + rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR_ISR));
1028 + seq_printf(m, "[11.3]R_AX_BBRPT_DFS_ERR_IMR_ISR=0x%08x\n",
1029 + rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR_ISR));
1030 + seq_printf(m, "[11.4]R_AX_LA_ERRFLAG=0x%08x\n",
1031 + rtw89_read32(rtwdev, R_AX_LA_ERRFLAG));
1032 +
1033 + return 0;
1034 +}
1035 +
1036 +static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev,
1037 + struct seq_file *m)
1038 +{
1039 + int ret;
1040 +
1041 + ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL);
1042 + if (ret) {
1043 + seq_puts(m, "[CMAC] : CMAC 0 not enabled\n");
1044 + return ret;
1045 + }
1046 +
1047 + seq_printf(m, "R_AX_CMAC_ERR_ISR=0x%08x\n",
1048 + rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR));
1049 + seq_printf(m, "[0]R_AX_SCHEDULE_ERR_ISR=0x%08x\n",
1050 + rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR));
1051 + seq_printf(m, "[1]R_AX_PTCL_ISR0=0x%08x\n",
1052 + rtw89_read32(rtwdev, R_AX_PTCL_ISR0));
1053 + seq_printf(m, "[3]R_AX_DLE_CTRL=0x%08x\n",
1054 + rtw89_read32(rtwdev, R_AX_DLE_CTRL));
1055 + seq_printf(m, "[4]R_AX_PHYINFO_ERR_ISR=0x%08x\n",
1056 + rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR));
1057 + seq_printf(m, "[5]R_AX_TXPWR_ISR=0x%08x\n",
1058 + rtw89_read32(rtwdev, R_AX_TXPWR_ISR));
1059 + seq_printf(m, "[6]R_AX_RMAC_ERR_ISR=0x%08x\n",
1060 + rtw89_read32(rtwdev, R_AX_RMAC_ERR_ISR));
1061 + seq_printf(m, "[7]R_AX_TMAC_ERR_IMR_ISR=0x%08x\n",
1062 + rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR));
1063 +
1064 + ret = rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL);
1065 + if (ret) {
1066 + seq_puts(m, "[CMAC] : CMAC 1 not enabled\n");
1067 + return ret;
1068 + }
1069 +
1070 + seq_printf(m, "R_AX_CMAC_ERR_ISR_C1=0x%08x\n",
1071 + rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR_C1));
1072 + seq_printf(m, "[0]R_AX_SCHEDULE_ERR_ISR_C1=0x%08x\n",
1073 + rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR_C1));
1074 + seq_printf(m, "[1]R_AX_PTCL_ISR0_C1=0x%08x\n",
1075 + rtw89_read32(rtwdev, R_AX_PTCL_ISR0_C1));
1076 + seq_printf(m, "[3]R_AX_DLE_CTRL_C1=0x%08x\n",
1077 + rtw89_read32(rtwdev, R_AX_DLE_CTRL_C1));
1078 + seq_printf(m, "[4]R_AX_PHYINFO_ERR_ISR_C1=0x%02x\n",
1079 + rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR_C1));
1080 + seq_printf(m, "[5]R_AX_TXPWR_ISR_C1=0x%08x\n",
1081 + rtw89_read32(rtwdev, R_AX_TXPWR_ISR_C1));
1082 + seq_printf(m, "[6]R_AX_RMAC_ERR_ISR_C1=0x%08x\n",
1083 + rtw89_read32(rtwdev, R_AX_RMAC_ERR_ISR_C1));
1084 + seq_printf(m, "[7]R_AX_TMAC_ERR_IMR_ISR_C1=0x%08x\n",
1085 + rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR_C1));
1086 +
1087 + return 0;
1088 +}
1089 +
1090 +static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c0 = {
1091 + .sel_addr = R_AX_PTCL_DBG,
1092 + .sel_byte = 1,
1093 + .sel_msk = B_AX_PTCL_DBG_SEL_MASK,
1094 + .srt = 0x00,
1095 + .end = 0x3F,
1096 + .rd_addr = R_AX_PTCL_DBG_INFO,
1097 + .rd_byte = 4,
1098 + .rd_msk = B_AX_PTCL_DBG_INFO_MASK
1099 +};
1100 +
1101 +static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c1 = {
1102 + .sel_addr = R_AX_PTCL_DBG_C1,
1103 + .sel_byte = 1,
1104 + .sel_msk = B_AX_PTCL_DBG_SEL_MASK,
1105 + .srt = 0x00,
1106 + .end = 0x3F,
1107 + .rd_addr = R_AX_PTCL_DBG_INFO_C1,
1108 + .rd_byte = 4,
1109 + .rd_msk = B_AX_PTCL_DBG_INFO_MASK
1110 +};
1111 +
1112 +static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = {
1113 + .sel_addr = R_AX_SCH_DBG_SEL,
1114 + .sel_byte = 1,
1115 + .sel_msk = B_AX_SCH_DBG_SEL_MASK,
1116 + .srt = 0x00,
1117 + .end = 0x2F,
1118 + .rd_addr = R_AX_SCH_DBG,
1119 + .rd_byte = 4,
1120 + .rd_msk = B_AX_SCHEDULER_DBG_MASK
1121 +};
1122 +
1123 +static const struct rtw89_mac_dbg_port_info dbg_port_sch_c1 = {
1124 + .sel_addr = R_AX_SCH_DBG_SEL_C1,
1125 + .sel_byte = 1,
1126 + .sel_msk = B_AX_SCH_DBG_SEL_MASK,
1127 + .srt = 0x00,
1128 + .end = 0x2F,
1129 + .rd_addr = R_AX_SCH_DBG_C1,
1130 + .rd_byte = 4,
1131 + .rd_msk = B_AX_SCHEDULER_DBG_MASK
1132 +};
1133 +
1134 +static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c0 = {
1135 + .sel_addr = R_AX_MACTX_DBG_SEL_CNT,
1136 + .sel_byte = 1,
1137 + .sel_msk = B_AX_DBGSEL_MACTX_MASK,
1138 + .srt = 0x00,
1139 + .end = 0x19,
1140 + .rd_addr = R_AX_DBG_PORT_SEL,
1141 + .rd_byte = 4,
1142 + .rd_msk = B_AX_DEBUG_ST_MASK
1143 +};
1144 +
1145 +static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c1 = {
1146 + .sel_addr = R_AX_MACTX_DBG_SEL_CNT_C1,
1147 + .sel_byte = 1,
1148 + .sel_msk = B_AX_DBGSEL_MACTX_MASK,
1149 + .srt = 0x00,
1150 + .end = 0x19,
1151 + .rd_addr = R_AX_DBG_PORT_SEL,
1152 + .rd_byte = 4,
1153 + .rd_msk = B_AX_DEBUG_ST_MASK
1154 +};
1155 +
1156 +static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c0 = {
1157 + .sel_addr = R_AX_RX_DEBUG_SELECT,
1158 + .sel_byte = 1,
1159 + .sel_msk = B_AX_DEBUG_SEL_MASK,
1160 + .srt = 0x00,
1161 + .end = 0x58,
1162 + .rd_addr = R_AX_DBG_PORT_SEL,
1163 + .rd_byte = 4,
1164 + .rd_msk = B_AX_DEBUG_ST_MASK
1165 +};
1166 +
1167 +static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c1 = {
1168 + .sel_addr = R_AX_RX_DEBUG_SELECT_C1,
1169 + .sel_byte = 1,
1170 + .sel_msk = B_AX_DEBUG_SEL_MASK,
1171 + .srt = 0x00,
1172 + .end = 0x58,
1173 + .rd_addr = R_AX_DBG_PORT_SEL,
1174 + .rd_byte = 4,
1175 + .rd_msk = B_AX_DEBUG_ST_MASK
1176 +};
1177 +
1178 +static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c0 = {
1179 + .sel_addr = R_AX_RX_STATE_MONITOR,
1180 + .sel_byte = 1,
1181 + .sel_msk = B_AX_STATE_SEL_MASK,
1182 + .srt = 0x00,
1183 + .end = 0x17,
1184 + .rd_addr = R_AX_RX_STATE_MONITOR,
1185 + .rd_byte = 4,
1186 + .rd_msk = B_AX_RX_STATE_MONITOR_MASK
1187 +};
1188 +
1189 +static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c1 = {
1190 + .sel_addr = R_AX_RX_STATE_MONITOR_C1,
1191 + .sel_byte = 1,
1192 + .sel_msk = B_AX_STATE_SEL_MASK,
1193 + .srt = 0x00,
1194 + .end = 0x17,
1195 + .rd_addr = R_AX_RX_STATE_MONITOR_C1,
1196 + .rd_byte = 4,
1197 + .rd_msk = B_AX_RX_STATE_MONITOR_MASK
1198 +};
1199 +
1200 +static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c0 = {
1201 + .sel_addr = R_AX_RMAC_PLCP_MON,
1202 + .sel_byte = 4,
1203 + .sel_msk = B_AX_PCLP_MON_SEL_MASK,
1204 + .srt = 0x0,
1205 + .end = 0xF,
1206 + .rd_addr = R_AX_RMAC_PLCP_MON,
1207 + .rd_byte = 4,
1208 + .rd_msk = B_AX_RMAC_PLCP_MON_MASK
1209 +};
1210 +
1211 +static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c1 = {
1212 + .sel_addr = R_AX_RMAC_PLCP_MON_C1,
1213 + .sel_byte = 4,
1214 + .sel_msk = B_AX_PCLP_MON_SEL_MASK,
1215 + .srt = 0x0,
1216 + .end = 0xF,
1217 + .rd_addr = R_AX_RMAC_PLCP_MON_C1,
1218 + .rd_byte = 4,
1219 + .rd_msk = B_AX_RMAC_PLCP_MON_MASK
1220 +};
1221 +
1222 +static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c0 = {
1223 + .sel_addr = R_AX_DBGSEL_TRXPTCL,
1224 + .sel_byte = 1,
1225 + .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK,
1226 + .srt = 0x08,
1227 + .end = 0x10,
1228 + .rd_addr = R_AX_DBG_PORT_SEL,
1229 + .rd_byte = 4,
1230 + .rd_msk = B_AX_DEBUG_ST_MASK
1231 +};
1232 +
1233 +static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c1 = {
1234 + .sel_addr = R_AX_DBGSEL_TRXPTCL_C1,
1235 + .sel_byte = 1,
1236 + .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK,
1237 + .srt = 0x08,
1238 + .end = 0x10,
1239 + .rd_addr = R_AX_DBG_PORT_SEL,
1240 + .rd_byte = 4,
1241 + .rd_msk = B_AX_DEBUG_ST_MASK
1242 +};
1243 +
1244 +static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c0 = {
1245 + .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG,
1246 + .sel_byte = 1,
1247 + .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK,
1248 + .srt = 0x00,
1249 + .end = 0x07,
1250 + .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG,
1251 + .rd_byte = 4,
1252 + .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK
1253 +};
1254 +
1255 +static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c0 = {
1256 + .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG,
1257 + .sel_byte = 1,
1258 + .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK,
1259 + .srt = 0x00,
1260 + .end = 0x07,
1261 + .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG,
1262 + .rd_byte = 4,
1263 + .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK
1264 +};
1265 +
1266 +static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c1 = {
1267 + .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1,
1268 + .sel_byte = 1,
1269 + .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK,
1270 + .srt = 0x00,
1271 + .end = 0x07,
1272 + .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG_C1,
1273 + .rd_byte = 4,
1274 + .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK
1275 +};
1276 +
1277 +static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c1 = {
1278 + .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1,
1279 + .sel_byte = 1,
1280 + .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK,
1281 + .srt = 0x00,
1282 + .end = 0x07,
1283 + .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG_C1,
1284 + .rd_byte = 4,
1285 + .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK
1286 +};
1287 +
1288 +static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c0 = {
1289 + .sel_addr = R_AX_WMAC_TX_TF_INFO_0,
1290 + .sel_byte = 1,
1291 + .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK,
1292 + .srt = 0x00,
1293 + .end = 0x04,
1294 + .rd_addr = R_AX_WMAC_TX_TF_INFO_1,
1295 + .rd_byte = 4,
1296 + .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK
1297 +};
1298 +
1299 +static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c0 = {
1300 + .sel_addr = R_AX_WMAC_TX_TF_INFO_0,
1301 + .sel_byte = 1,
1302 + .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK,
1303 + .srt = 0x00,
1304 + .end = 0x04,
1305 + .rd_addr = R_AX_WMAC_TX_TF_INFO_2,
1306 + .rd_byte = 4,
1307 + .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK
1308 +};
1309 +
1310 +static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c1 = {
1311 + .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1,
1312 + .sel_byte = 1,
1313 + .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK,
1314 + .srt = 0x00,
1315 + .end = 0x04,
1316 + .rd_addr = R_AX_WMAC_TX_TF_INFO_1_C1,
1317 + .rd_byte = 4,
1318 + .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK
1319 +};
1320 +
1321 +static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c1 = {
1322 + .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1,
1323 + .sel_byte = 1,
1324 + .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK,
1325 + .srt = 0x00,
1326 + .end = 0x04,
1327 + .rd_addr = R_AX_WMAC_TX_TF_INFO_2_C1,
1328 + .rd_byte = 4,
1329 + .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK
1330 +};
1331 +
1332 +static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_freepg = {
1333 + .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1334 + .sel_byte = 4,
1335 + .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1336 + .srt = 0x80000000,
1337 + .end = 0x80000001,
1338 + .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
1339 + .rd_byte = 4,
1340 + .rd_msk = B_AX_WDE_DFI_DATA_MASK
1341 +};
1342 +
1343 +static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_quota = {
1344 + .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1345 + .sel_byte = 4,
1346 + .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1347 + .srt = 0x80010000,
1348 + .end = 0x80010004,
1349 + .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
1350 + .rd_byte = 4,
1351 + .rd_msk = B_AX_WDE_DFI_DATA_MASK
1352 +};
1353 +
1354 +static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pagellt = {
1355 + .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1356 + .sel_byte = 4,
1357 + .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1358 + .srt = 0x80020000,
1359 + .end = 0x80020FFF,
1360 + .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
1361 + .rd_byte = 4,
1362 + .rd_msk = B_AX_WDE_DFI_DATA_MASK
1363 +};
1364 +
1365 +static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pktinfo = {
1366 + .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1367 + .sel_byte = 4,
1368 + .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1369 + .srt = 0x80030000,
1370 + .end = 0x80030FFF,
1371 + .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
1372 + .rd_byte = 4,
1373 + .rd_msk = B_AX_WDE_DFI_DATA_MASK
1374 +};
1375 +
1376 +static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_prepkt = {
1377 + .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1378 + .sel_byte = 4,
1379 + .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1380 + .srt = 0x80040000,
1381 + .end = 0x80040FFF,
1382 + .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
1383 + .rd_byte = 4,
1384 + .rd_msk = B_AX_WDE_DFI_DATA_MASK
1385 +};
1386 +
1387 +static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_nxtpkt = {
1388 + .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1389 + .sel_byte = 4,
1390 + .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1391 + .srt = 0x80050000,
1392 + .end = 0x80050FFF,
1393 + .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
1394 + .rd_byte = 4,
1395 + .rd_msk = B_AX_WDE_DFI_DATA_MASK
1396 +};
1397 +
1398 +static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qlnktbl = {
1399 + .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1400 + .sel_byte = 4,
1401 + .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1402 + .srt = 0x80060000,
1403 + .end = 0x80060453,
1404 + .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
1405 + .rd_byte = 4,
1406 + .rd_msk = B_AX_WDE_DFI_DATA_MASK
1407 +};
1408 +
1409 +static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qempty = {
1410 + .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1411 + .sel_byte = 4,
1412 + .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1413 + .srt = 0x80070000,
1414 + .end = 0x80070011,
1415 + .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
1416 + .rd_byte = 4,
1417 + .rd_msk = B_AX_WDE_DFI_DATA_MASK
1418 +};
1419 +
1420 +static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_freepg = {
1421 + .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
1422 + .sel_byte = 4,
1423 + .sel_msk = B_AX_PLE_DFI_DATA_MASK,
1424 + .srt = 0x80000000,
1425 + .end = 0x80000001,
1426 + .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
1427 + .rd_byte = 4,
1428 + .rd_msk = B_AX_PLE_DFI_DATA_MASK
1429 +};
1430 +
1431 +static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_quota = {
1432 + .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
1433 + .sel_byte = 4,
1434 + .sel_msk = B_AX_PLE_DFI_DATA_MASK,
1435 + .srt = 0x80010000,
1436 + .end = 0x8001000A,
1437 + .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
1438 + .rd_byte = 4,
1439 + .rd_msk = B_AX_PLE_DFI_DATA_MASK
1440 +};
1441 +
1442 +static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pagellt = {
1443 + .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
1444 + .sel_byte = 4,
1445 + .sel_msk = B_AX_PLE_DFI_DATA_MASK,
1446 + .srt = 0x80020000,
1447 + .end = 0x80020DBF,
1448 + .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
1449 + .rd_byte = 4,
1450 + .rd_msk = B_AX_PLE_DFI_DATA_MASK
1451 +};
1452 +
1453 +static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pktinfo = {
1454 + .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
1455 + .sel_byte = 4,
1456 + .sel_msk = B_AX_PLE_DFI_DATA_MASK,
1457 + .srt = 0x80030000,
1458 + .end = 0x80030DBF,
1459 + .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
1460 + .rd_byte = 4,
1461 + .rd_msk = B_AX_PLE_DFI_DATA_MASK
1462 +};
1463 +
1464 +static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_prepkt = {
1465 + .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
1466 + .sel_byte = 4,
1467 + .sel_msk = B_AX_PLE_DFI_DATA_MASK,
1468 + .srt = 0x80040000,
1469 + .end = 0x80040DBF,
1470 + .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
1471 + .rd_byte = 4,
1472 + .rd_msk = B_AX_PLE_DFI_DATA_MASK
1473 +};
1474 +
1475 +static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_nxtpkt = {
1476 + .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
1477 + .sel_byte = 4,
1478 + .sel_msk = B_AX_PLE_DFI_DATA_MASK,
1479 + .srt = 0x80050000,
1480 + .end = 0x80050DBF,
1481 + .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
1482 + .rd_byte = 4,
1483 + .rd_msk = B_AX_PLE_DFI_DATA_MASK
1484 +};
1485 +
1486 +static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qlnktbl = {
1487 + .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
1488 + .sel_byte = 4,
1489 + .sel_msk = B_AX_PLE_DFI_DATA_MASK,
1490 + .srt = 0x80060000,
1491 + .end = 0x80060041,
1492 + .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
1493 + .rd_byte = 4,
1494 + .rd_msk = B_AX_PLE_DFI_DATA_MASK
1495 +};
1496 +
1497 +static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qempty = {
1498 + .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
1499 + .sel_byte = 4,
1500 + .sel_msk = B_AX_PLE_DFI_DATA_MASK,
1501 + .srt = 0x80070000,
1502 + .end = 0x80070001,
1503 + .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
1504 + .rd_byte = 4,
1505 + .rd_msk = B_AX_PLE_DFI_DATA_MASK
1506 +};
1507 +
1508 +static const struct rtw89_mac_dbg_port_info dbg_port_pktinfo = {
1509 + .sel_addr = R_AX_DBG_FUN_INTF_CTL,
1510 + .sel_byte = 4,
1511 + .sel_msk = B_AX_DFI_DATA_MASK,
1512 + .srt = 0x80000000,
1513 + .end = 0x8000017f,
1514 + .rd_addr = R_AX_DBG_FUN_INTF_DATA,
1515 + .rd_byte = 4,
1516 + .rd_msk = B_AX_DFI_DATA_MASK
1517 +};
1518 +
1519 +static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = {
1520 + .sel_addr = R_AX_PCIE_DBG_CTRL,
1521 + .sel_byte = 2,
1522 + .sel_msk = B_AX_DBG_SEL_MASK,
1523 + .srt = 0x00,
1524 + .end = 0x03,
1525 + .rd_addr = R_AX_DBG_PORT_SEL,
1526 + .rd_byte = 4,
1527 + .rd_msk = B_AX_DEBUG_ST_MASK
1528 +};
1529 +
1530 +static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = {
1531 + .sel_addr = R_AX_PCIE_DBG_CTRL,
1532 + .sel_byte = 2,
1533 + .sel_msk = B_AX_DBG_SEL_MASK,
1534 + .srt = 0x00,
1535 + .end = 0x04,
1536 + .rd_addr = R_AX_DBG_PORT_SEL,
1537 + .rd_byte = 4,
1538 + .rd_msk = B_AX_DEBUG_ST_MASK
1539 +};
1540 +
1541 +static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = {
1542 + .sel_addr = R_AX_PCIE_DBG_CTRL,
1543 + .sel_byte = 2,
1544 + .sel_msk = B_AX_DBG_SEL_MASK,
1545 + .srt = 0x00,
1546 + .end = 0x01,
1547 + .rd_addr = R_AX_DBG_PORT_SEL,
1548 + .rd_byte = 4,
1549 + .rd_msk = B_AX_DEBUG_ST_MASK
1550 +};
1551 +
1552 +static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = {
1553 + .sel_addr = R_AX_PCIE_DBG_CTRL,
1554 + .sel_byte = 2,
1555 + .sel_msk = B_AX_DBG_SEL_MASK,
1556 + .srt = 0x00,
1557 + .end = 0x05,
1558 + .rd_addr = R_AX_DBG_PORT_SEL,
1559 + .rd_byte = 4,
1560 + .rd_msk = B_AX_DEBUG_ST_MASK
1561 +};
1562 +
1563 +static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = {
1564 + .sel_addr = R_AX_PCIE_DBG_CTRL,
1565 + .sel_byte = 2,
1566 + .sel_msk = B_AX_DBG_SEL_MASK,
1567 + .srt = 0x00,
1568 + .end = 0x05,
1569 + .rd_addr = R_AX_DBG_PORT_SEL,
1570 + .rd_byte = 4,
1571 + .rd_msk = B_AX_DEBUG_ST_MASK
1572 +};
1573 +
1574 +static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = {
1575 + .sel_addr = R_AX_PCIE_DBG_CTRL,
1576 + .sel_byte = 2,
1577 + .sel_msk = B_AX_DBG_SEL_MASK,
1578 + .srt = 0x00,
1579 + .end = 0x06,
1580 + .rd_addr = R_AX_DBG_PORT_SEL,
1581 + .rd_byte = 4,
1582 + .rd_msk = B_AX_DEBUG_ST_MASK
1583 +};
1584 +
1585 +static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc2 = {
1586 + .sel_addr = R_AX_DBG_CTRL,
1587 + .sel_byte = 1,
1588 + .sel_msk = B_AX_DBG_SEL0,
1589 + .srt = 0x34,
1590 + .end = 0x3C,
1591 + .rd_addr = R_AX_DBG_PORT_SEL,
1592 + .rd_byte = 4,
1593 + .rd_msk = B_AX_DEBUG_ST_MASK
1594 +};
1595 +
1596 +static const struct rtw89_mac_dbg_port_info *
1597 +rtw89_debug_mac_dbg_port_sel(struct seq_file *m,
1598 + struct rtw89_dev *rtwdev, u32 sel)
1599 +{
1600 + const struct rtw89_mac_dbg_port_info *info;
1601 + u32 val32;
1602 + u16 val16;
1603 + u8 val8;
1604 +
1605 + switch (sel) {
1606 + case RTW89_DBG_PORT_SEL_PTCL_C0:
1607 + info = &dbg_port_ptcl_c0;
1608 + val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG);
1609 + val16 |= B_AX_PTCL_DBG_EN;
1610 + rtw89_write16(rtwdev, R_AX_PTCL_DBG, val16);
1611 + seq_puts(m, "Enable PTCL C0 dbgport.\n");
1612 + break;
1613 + case RTW89_DBG_PORT_SEL_PTCL_C1:
1614 + info = &dbg_port_ptcl_c1;
1615 + val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG_C1);
1616 + val16 |= B_AX_PTCL_DBG_EN;
1617 + rtw89_write16(rtwdev, R_AX_PTCL_DBG_C1, val16);
1618 + seq_puts(m, "Enable PTCL C1 dbgport.\n");
1619 + break;
1620 + case RTW89_DBG_PORT_SEL_SCH_C0:
1621 + info = &dbg_port_sch_c0;
1622 + val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL);
1623 + val32 |= B_AX_SCH_DBG_EN;
1624 + rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL, val32);
1625 + seq_puts(m, "Enable SCH C0 dbgport.\n");
1626 + break;
1627 + case RTW89_DBG_PORT_SEL_SCH_C1:
1628 + info = &dbg_port_sch_c1;
1629 + val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL_C1);
1630 + val32 |= B_AX_SCH_DBG_EN;
1631 + rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL_C1, val32);
1632 + seq_puts(m, "Enable SCH C1 dbgport.\n");
1633 + break;
1634 + case RTW89_DBG_PORT_SEL_TMAC_C0:
1635 + info = &dbg_port_tmac_c0;
1636 + val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL);
1637 + val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC,
1638 + B_AX_DBGSEL_TRXPTCL_MASK);
1639 + rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32);
1640 +
1641 + val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1642 + val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0);
1643 + val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1);
1644 + rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1645 +
1646 + val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
1647 + val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
1648 + rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
1649 + seq_puts(m, "Enable TMAC C0 dbgport.\n");
1650 + break;
1651 + case RTW89_DBG_PORT_SEL_TMAC_C1:
1652 + info = &dbg_port_tmac_c1;
1653 + val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1);
1654 + val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC,
1655 + B_AX_DBGSEL_TRXPTCL_MASK);
1656 + rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32);
1657 +
1658 + val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1659 + val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0);
1660 + val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1);
1661 + rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1662 +
1663 + val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
1664 + val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
1665 + rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
1666 + seq_puts(m, "Enable TMAC C1 dbgport.\n");
1667 + break;
1668 + case RTW89_DBG_PORT_SEL_RMAC_C0:
1669 + info = &dbg_port_rmac_c0;
1670 + val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL);
1671 + val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC,
1672 + B_AX_DBGSEL_TRXPTCL_MASK);
1673 + rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32);
1674 +
1675 + val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1676 + val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0);
1677 + val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1);
1678 + rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1679 +
1680 + val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
1681 + val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
1682 + rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
1683 +
1684 + val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL);
1685 + val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL,
1686 + B_AX_DBGSEL_TRXPTCL_MASK);
1687 + rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL, val8);
1688 + seq_puts(m, "Enable RMAC C0 dbgport.\n");
1689 + break;
1690 + case RTW89_DBG_PORT_SEL_RMAC_C1:
1691 + info = &dbg_port_rmac_c1;
1692 + val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1);
1693 + val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC,
1694 + B_AX_DBGSEL_TRXPTCL_MASK);
1695 + rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32);
1696 +
1697 + val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1698 + val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0);
1699 + val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1);
1700 + rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1701 +
1702 + val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
1703 + val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
1704 + rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
1705 +
1706 + val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1);
1707 + val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL,
1708 + B_AX_DBGSEL_TRXPTCL_MASK);
1709 + rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val8);
1710 + seq_puts(m, "Enable RMAC C1 dbgport.\n");
1711 + break;
1712 + case RTW89_DBG_PORT_SEL_RMACST_C0:
1713 + info = &dbg_port_rmacst_c0;
1714 + seq_puts(m, "Enable RMAC state C0 dbgport.\n");
1715 + break;
1716 + case RTW89_DBG_PORT_SEL_RMACST_C1:
1717 + info = &dbg_port_rmacst_c1;
1718 + seq_puts(m, "Enable RMAC state C1 dbgport.\n");
1719 + break;
1720 + case RTW89_DBG_PORT_SEL_RMAC_PLCP_C0:
1721 + info = &dbg_port_rmac_plcp_c0;
1722 + seq_puts(m, "Enable RMAC PLCP C0 dbgport.\n");
1723 + break;
1724 + case RTW89_DBG_PORT_SEL_RMAC_PLCP_C1:
1725 + info = &dbg_port_rmac_plcp_c1;
1726 + seq_puts(m, "Enable RMAC PLCP C1 dbgport.\n");
1727 + break;
1728 + case RTW89_DBG_PORT_SEL_TRXPTCL_C0:
1729 + info = &dbg_port_trxptcl_c0;
1730 + val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1731 + val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0);
1732 + val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1);
1733 + rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1734 +
1735 + val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
1736 + val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
1737 + rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
1738 + seq_puts(m, "Enable TRXPTCL C0 dbgport.\n");
1739 + break;
1740 + case RTW89_DBG_PORT_SEL_TRXPTCL_C1:
1741 + info = &dbg_port_trxptcl_c1;
1742 + val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1743 + val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0);
1744 + val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1);
1745 + rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1746 +
1747 + val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
1748 + val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
1749 + rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
1750 + seq_puts(m, "Enable TRXPTCL C1 dbgport.\n");
1751 + break;
1752 + case RTW89_DBG_PORT_SEL_TX_INFOL_C0:
1753 + info = &dbg_port_tx_infol_c0;
1754 + val32 = rtw89_read32(rtwdev, R_AX_TCR1);
1755 + val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
1756 + rtw89_write32(rtwdev, R_AX_TCR1, val32);
1757 + seq_puts(m, "Enable tx infol dump.\n");
1758 + break;
1759 + case RTW89_DBG_PORT_SEL_TX_INFOH_C0:
1760 + info = &dbg_port_tx_infoh_c0;
1761 + val32 = rtw89_read32(rtwdev, R_AX_TCR1);
1762 + val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
1763 + rtw89_write32(rtwdev, R_AX_TCR1, val32);
1764 + seq_puts(m, "Enable tx infoh dump.\n");
1765 + break;
1766 + case RTW89_DBG_PORT_SEL_TX_INFOL_C1:
1767 + info = &dbg_port_tx_infol_c1;
1768 + val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1);
1769 + val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
1770 + rtw89_write32(rtwdev, R_AX_TCR1_C1, val32);
1771 + seq_puts(m, "Enable tx infol dump.\n");
1772 + break;
1773 + case RTW89_DBG_PORT_SEL_TX_INFOH_C1:
1774 + info = &dbg_port_tx_infoh_c1;
1775 + val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1);
1776 + val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
1777 + rtw89_write32(rtwdev, R_AX_TCR1_C1, val32);
1778 + seq_puts(m, "Enable tx infoh dump.\n");
1779 + break;
1780 + case RTW89_DBG_PORT_SEL_TXTF_INFOL_C0:
1781 + info = &dbg_port_txtf_infol_c0;
1782 + val32 = rtw89_read32(rtwdev, R_AX_TCR1);
1783 + val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
1784 + rtw89_write32(rtwdev, R_AX_TCR1, val32);
1785 + seq_puts(m, "Enable tx tf infol dump.\n");
1786 + break;
1787 + case RTW89_DBG_PORT_SEL_TXTF_INFOH_C0:
1788 + info = &dbg_port_txtf_infoh_c0;
1789 + val32 = rtw89_read32(rtwdev, R_AX_TCR1);
1790 + val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
1791 + rtw89_write32(rtwdev, R_AX_TCR1, val32);
1792 + seq_puts(m, "Enable tx tf infoh dump.\n");
1793 + break;
1794 + case RTW89_DBG_PORT_SEL_TXTF_INFOL_C1:
1795 + info = &dbg_port_txtf_infol_c1;
1796 + val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1);
1797 + val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
1798 + rtw89_write32(rtwdev, R_AX_TCR1_C1, val32);
1799 + seq_puts(m, "Enable tx tf infol dump.\n");
1800 + break;
1801 + case RTW89_DBG_PORT_SEL_TXTF_INFOH_C1:
1802 + info = &dbg_port_txtf_infoh_c1;
1803 + val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1);
1804 + val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
1805 + rtw89_write32(rtwdev, R_AX_TCR1_C1, val32);
1806 + seq_puts(m, "Enable tx tf infoh dump.\n");
1807 + break;
1808 + case RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG:
1809 + info = &dbg_port_wde_bufmgn_freepg;
1810 + seq_puts(m, "Enable wde bufmgn freepg dump.\n");
1811 + break;
1812 + case RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA:
1813 + info = &dbg_port_wde_bufmgn_quota;
1814 + seq_puts(m, "Enable wde bufmgn quota dump.\n");
1815 + break;
1816 + case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT:
1817 + info = &dbg_port_wde_bufmgn_pagellt;
1818 + seq_puts(m, "Enable wde bufmgn pagellt dump.\n");
1819 + break;
1820 + case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO:
1821 + info = &dbg_port_wde_bufmgn_pktinfo;
1822 + seq_puts(m, "Enable wde bufmgn pktinfo dump.\n");
1823 + break;
1824 + case RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT:
1825 + info = &dbg_port_wde_quemgn_prepkt;
1826 + seq_puts(m, "Enable wde quemgn prepkt dump.\n");
1827 + break;
1828 + case RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT:
1829 + info = &dbg_port_wde_quemgn_nxtpkt;
1830 + seq_puts(m, "Enable wde quemgn nxtpkt dump.\n");
1831 + break;
1832 + case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL:
1833 + info = &dbg_port_wde_quemgn_qlnktbl;
1834 + seq_puts(m, "Enable wde quemgn qlnktbl dump.\n");
1835 + break;
1836 + case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY:
1837 + info = &dbg_port_wde_quemgn_qempty;
1838 + seq_puts(m, "Enable wde quemgn qempty dump.\n");
1839 + break;
1840 + case RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG:
1841 + info = &dbg_port_ple_bufmgn_freepg;
1842 + seq_puts(m, "Enable ple bufmgn freepg dump.\n");
1843 + break;
1844 + case RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA:
1845 + info = &dbg_port_ple_bufmgn_quota;
1846 + seq_puts(m, "Enable ple bufmgn quota dump.\n");
1847 + break;
1848 + case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT:
1849 + info = &dbg_port_ple_bufmgn_pagellt;
1850 + seq_puts(m, "Enable ple bufmgn pagellt dump.\n");
1851 + break;
1852 + case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO:
1853 + info = &dbg_port_ple_bufmgn_pktinfo;
1854 + seq_puts(m, "Enable ple bufmgn pktinfo dump.\n");
1855 + break;
1856 + case RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT:
1857 + info = &dbg_port_ple_quemgn_prepkt;
1858 + seq_puts(m, "Enable ple quemgn prepkt dump.\n");
1859 + break;
1860 + case RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT:
1861 + info = &dbg_port_ple_quemgn_nxtpkt;
1862 + seq_puts(m, "Enable ple quemgn nxtpkt dump.\n");
1863 + break;
1864 + case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL:
1865 + info = &dbg_port_ple_quemgn_qlnktbl;
1866 + seq_puts(m, "Enable ple quemgn qlnktbl dump.\n");
1867 + break;
1868 + case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY:
1869 + info = &dbg_port_ple_quemgn_qempty;
1870 + seq_puts(m, "Enable ple quemgn qempty dump.\n");
1871 + break;
1872 + case RTW89_DBG_PORT_SEL_PKTINFO:
1873 + info = &dbg_port_pktinfo;
1874 + seq_puts(m, "Enable pktinfo dump.\n");
1875 + break;
1876 + case RTW89_DBG_PORT_SEL_PCIE_TXDMA:
1877 + info = &dbg_port_pcie_txdma;
1878 + val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1879 + val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0);
1880 + val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1);
1881 + rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1882 + seq_puts(m, "Enable pcie txdma dump.\n");
1883 + break;
1884 + case RTW89_DBG_PORT_SEL_PCIE_RXDMA:
1885 + info = &dbg_port_pcie_rxdma;
1886 + val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1887 + val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0);
1888 + val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1);
1889 + rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1890 + seq_puts(m, "Enable pcie rxdma dump.\n");
1891 + break;
1892 + case RTW89_DBG_PORT_SEL_PCIE_CVT:
1893 + info = &dbg_port_pcie_cvt;
1894 + val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1895 + val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0);
1896 + val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1);
1897 + rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1898 + seq_puts(m, "Enable pcie cvt dump.\n");
1899 + break;
1900 + case RTW89_DBG_PORT_SEL_PCIE_CXPL:
1901 + info = &dbg_port_pcie_cxpl;
1902 + val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1903 + val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL0);
1904 + val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL1);
1905 + rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1906 + seq_puts(m, "Enable pcie cxpl dump.\n");
1907 + break;
1908 + case RTW89_DBG_PORT_SEL_PCIE_IO:
1909 + info = &dbg_port_pcie_io;
1910 + val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1911 + val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL0);
1912 + val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL1);
1913 + rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1914 + seq_puts(m, "Enable pcie io dump.\n");
1915 + break;
1916 + case RTW89_DBG_PORT_SEL_PCIE_MISC:
1917 + info = &dbg_port_pcie_misc;
1918 + val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1919 + val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL0);
1920 + val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL1);
1921 + rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1922 + seq_puts(m, "Enable pcie misc dump.\n");
1923 + break;
1924 + case RTW89_DBG_PORT_SEL_PCIE_MISC2:
1925 + info = &dbg_port_pcie_misc2;
1926 + val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL);
1927 + val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL,
1928 + B_AX_DBG_SEL_MASK);
1929 + rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16);
1930 + seq_puts(m, "Enable pcie misc2 dump.\n");
1931 + break;
1932 + default:
1933 + seq_puts(m, "Dbg port select err\n");
1934 + return NULL;
1935 + }
1936 +
1937 + return info;
1938 +}
1939 +
1940 +static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel)
1941 +{
1942 + if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE &&
1943 + sel >= RTW89_DBG_PORT_SEL_PCIE_TXDMA &&
1944 + sel <= RTW89_DBG_PORT_SEL_PCIE_MISC2)
1945 + return false;
1946 + if (rtwdev->chip->chip_id == RTL8852B &&
1947 + sel >= RTW89_DBG_PORT_SEL_PTCL_C1 &&
1948 + sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1)
1949 + return false;
1950 + if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) &&
1951 + sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG &&
1952 + sel <= RTW89_DBG_PORT_SEL_PKTINFO)
1953 + return false;
1954 + if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) &&
1955 + sel >= RTW89_DBG_PORT_SEL_PTCL_C0 &&
1956 + sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0)
1957 + return false;
1958 + if (rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL) &&
1959 + sel >= RTW89_DBG_PORT_SEL_PTCL_C1 &&
1960 + sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1)
1961 + return false;
1962 +
1963 + return true;
1964 +}
1965 +
1966 +static int rtw89_debug_mac_dbg_port_dump(struct rtw89_dev *rtwdev,
1967 + struct seq_file *m, u32 sel)
1968 +{
1969 + const struct rtw89_mac_dbg_port_info *info;
1970 + u8 val8;
1971 + u16 val16;
1972 + u32 val32;
1973 + u32 i;
1974 +
1975 + info = rtw89_debug_mac_dbg_port_sel(m, rtwdev, sel);
1976 + if (!info) {
1977 + rtw89_err(rtwdev, "failed to select debug port %d\n", sel);
1978 + return -EINVAL;
1979 + }
1980 +
1981 +#define case_DBG_SEL(__sel) \
1982 + case RTW89_DBG_PORT_SEL_##__sel: \
1983 + seq_puts(m, "Dump debug port " #__sel ":\n"); \
1984 + break
1985 +
1986 + switch (sel) {
1987 + case_DBG_SEL(PTCL_C0);
1988 + case_DBG_SEL(PTCL_C1);
1989 + case_DBG_SEL(SCH_C0);
1990 + case_DBG_SEL(SCH_C1);
1991 + case_DBG_SEL(TMAC_C0);
1992 + case_DBG_SEL(TMAC_C1);
1993 + case_DBG_SEL(RMAC_C0);
1994 + case_DBG_SEL(RMAC_C1);
1995 + case_DBG_SEL(RMACST_C0);
1996 + case_DBG_SEL(RMACST_C1);
1997 + case_DBG_SEL(TRXPTCL_C0);
1998 + case_DBG_SEL(TRXPTCL_C1);
1999 + case_DBG_SEL(TX_INFOL_C0);
2000 + case_DBG_SEL(TX_INFOH_C0);
2001 + case_DBG_SEL(TX_INFOL_C1);
2002 + case_DBG_SEL(TX_INFOH_C1);
2003 + case_DBG_SEL(TXTF_INFOL_C0);
2004 + case_DBG_SEL(TXTF_INFOH_C0);
2005 + case_DBG_SEL(TXTF_INFOL_C1);
2006 + case_DBG_SEL(TXTF_INFOH_C1);
2007 + case_DBG_SEL(WDE_BUFMGN_FREEPG);
2008 + case_DBG_SEL(WDE_BUFMGN_QUOTA);
2009 + case_DBG_SEL(WDE_BUFMGN_PAGELLT);
2010 + case_DBG_SEL(WDE_BUFMGN_PKTINFO);
2011 + case_DBG_SEL(WDE_QUEMGN_PREPKT);
2012 + case_DBG_SEL(WDE_QUEMGN_NXTPKT);
2013 + case_DBG_SEL(WDE_QUEMGN_QLNKTBL);
2014 + case_DBG_SEL(WDE_QUEMGN_QEMPTY);
2015 + case_DBG_SEL(PLE_BUFMGN_FREEPG);
2016 + case_DBG_SEL(PLE_BUFMGN_QUOTA);
2017 + case_DBG_SEL(PLE_BUFMGN_PAGELLT);
2018 + case_DBG_SEL(PLE_BUFMGN_PKTINFO);
2019 + case_DBG_SEL(PLE_QUEMGN_PREPKT);
2020 + case_DBG_SEL(PLE_QUEMGN_NXTPKT);
2021 + case_DBG_SEL(PLE_QUEMGN_QLNKTBL);
2022 + case_DBG_SEL(PLE_QUEMGN_QEMPTY);
2023 + case_DBG_SEL(PKTINFO);
2024 + case_DBG_SEL(PCIE_TXDMA);
2025 + case_DBG_SEL(PCIE_RXDMA);
2026 + case_DBG_SEL(PCIE_CVT);
2027 + case_DBG_SEL(PCIE_CXPL);
2028 + case_DBG_SEL(PCIE_IO);
2029 + case_DBG_SEL(PCIE_MISC);
2030 + case_DBG_SEL(PCIE_MISC2);
2031 + }
2032 +
2033 +#undef case_DBG_SEL
2034 +
2035 + seq_printf(m, "Sel addr = 0x%X\n", info->sel_addr);
2036 + seq_printf(m, "Read addr = 0x%X\n", info->rd_addr);
2037 +
2038 + for (i = info->srt; i <= info->end; i++) {
2039 + switch (info->sel_byte) {
2040 + case 1:
2041 + default:
2042 + rtw89_write8_mask(rtwdev, info->sel_addr,
2043 + info->sel_msk, i);
2044 + seq_printf(m, "0x%02X: ", i);
2045 + break;
2046 + case 2:
2047 + rtw89_write16_mask(rtwdev, info->sel_addr,
2048 + info->sel_msk, i);
2049 + seq_printf(m, "0x%04X: ", i);
2050 + break;
2051 + case 4:
2052 + rtw89_write32_mask(rtwdev, info->sel_addr,
2053 + info->sel_msk, i);
2054 + seq_printf(m, "0x%04X: ", i);
2055 + break;
2056 + }
2057 +
2058 + udelay(10);
2059 +
2060 + switch (info->rd_byte) {
2061 + case 1:
2062 + default:
2063 + val8 = rtw89_read8_mask(rtwdev,
2064 + info->rd_addr, info->rd_msk);
2065 + seq_printf(m, "0x%02X\n", val8);
2066 + break;
2067 + case 2:
2068 + val16 = rtw89_read16_mask(rtwdev,
2069 + info->rd_addr, info->rd_msk);
2070 + seq_printf(m, "0x%04X\n", val16);
2071 + break;
2072 + case 4:
2073 + val32 = rtw89_read32_mask(rtwdev,
2074 + info->rd_addr, info->rd_msk);
2075 + seq_printf(m, "0x%08X\n", val32);
2076 + break;
2077 + }
2078 + }
2079 +
2080 + return 0;
2081 +}
2082 +
2083 +static int rtw89_debug_mac_dump_dbg_port(struct rtw89_dev *rtwdev,
2084 + struct seq_file *m)
2085 +{
2086 + u32 sel;
2087 + int ret = 0;
2088 +
2089 + for (sel = RTW89_DBG_PORT_SEL_PTCL_C0;
2090 + sel < RTW89_DBG_PORT_SEL_LAST; sel++) {
2091 + if (!is_dbg_port_valid(rtwdev, sel))
2092 + continue;
2093 + ret = rtw89_debug_mac_dbg_port_dump(rtwdev, m, sel);
2094 + if (ret) {
2095 + rtw89_err(rtwdev,
2096 + "failed to dump debug port %d\n", sel);
2097 + break;
2098 + }
2099 + }
2100 +
2101 + return ret;
2102 +}
2103 +
2104 +static int
2105 +rtw89_debug_priv_mac_dbg_port_dump_get(struct seq_file *m, void *v)
2106 +{
2107 + struct rtw89_debugfs_priv *debugfs_priv = m->private;
2108 + struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2109 +
2110 + if (debugfs_priv->dbgpkg_en.ss_dbg)
2111 + rtw89_debug_mac_dump_ss_dbg(rtwdev, m);
2112 + if (debugfs_priv->dbgpkg_en.dle_dbg)
2113 + rtw89_debug_mac_dump_dle_dbg(rtwdev, m);
2114 + if (debugfs_priv->dbgpkg_en.dmac_dbg)
2115 + rtw89_debug_mac_dump_dmac_dbg(rtwdev, m);
2116 + if (debugfs_priv->dbgpkg_en.cmac_dbg)
2117 + rtw89_debug_mac_dump_cmac_dbg(rtwdev, m);
2118 + if (debugfs_priv->dbgpkg_en.dbg_port)
2119 + rtw89_debug_mac_dump_dbg_port(rtwdev, m);
2120 +
2121 + return 0;
2122 +};
2123 +
2124 +static u8 *rtw89_hex2bin_user(struct rtw89_dev *rtwdev,
2125 + const char __user *user_buf, size_t count)
2126 +{
2127 + char *buf;
2128 + u8 *bin;
2129 + int num;
2130 + int err = 0;
2131 +
2132 + buf = memdup_user(user_buf, count);
2133 + if (IS_ERR(buf))
2134 + return buf;
2135 +
2136 + num = count / 2;
2137 + bin = kmalloc(num, GFP_KERNEL);
2138 + if (!bin) {
2139 + err = -EFAULT;
2140 + goto out;
2141 + }
2142 +
2143 + if (hex2bin(bin, buf, num)) {
2144 + rtw89_info(rtwdev, "valid format: H1H2H3...\n");
2145 + kfree(bin);
2146 + err = -EINVAL;
2147 + }
2148 +
2149 +out:
2150 + kfree(buf);
2151 +
2152 + return err ? ERR_PTR(err) : bin;
2153 +}
2154 +
2155 +static ssize_t rtw89_debug_priv_send_h2c_set(struct file *filp,
2156 + const char __user *user_buf,
2157 + size_t count, loff_t *loff)
2158 +{
2159 + struct rtw89_debugfs_priv *debugfs_priv = filp->private_data;
2160 + struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2161 + u8 *h2c;
2162 + u16 h2c_len = count / 2;
2163 +
2164 + h2c = rtw89_hex2bin_user(rtwdev, user_buf, count);
2165 + if (IS_ERR(h2c))
2166 + return -EFAULT;
2167 +
2168 + rtw89_fw_h2c_raw(rtwdev, h2c, h2c_len);
2169 +
2170 + kfree(h2c);
2171 +
2172 + return count;
2173 +}
2174 +
2175 +static int
2176 +rtw89_debug_priv_early_h2c_get(struct seq_file *m, void *v)
2177 +{
2178 + struct rtw89_debugfs_priv *debugfs_priv = m->private;
2179 + struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2180 + struct rtw89_early_h2c *early_h2c;
2181 + int seq = 0;
2182 +
2183 + mutex_lock(&rtwdev->mutex);
2184 + list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list)
2185 + seq_printf(m, "%d: %*ph\n", ++seq, early_h2c->h2c_len, early_h2c->h2c);
2186 + mutex_unlock(&rtwdev->mutex);
2187 +
2188 + return 0;
2189 +}
2190 +
2191 +static ssize_t
2192 +rtw89_debug_priv_early_h2c_set(struct file *filp, const char __user *user_buf,
2193 + size_t count, loff_t *loff)
2194 +{
2195 + struct seq_file *m = (struct seq_file *)filp->private_data;
2196 + struct rtw89_debugfs_priv *debugfs_priv = m->private;
2197 + struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2198 + struct rtw89_early_h2c *early_h2c;
2199 + u8 *h2c;
2200 + u16 h2c_len = count / 2;
2201 +
2202 + h2c = rtw89_hex2bin_user(rtwdev, user_buf, count);
2203 + if (IS_ERR(h2c))
2204 + return -EFAULT;
2205 +
2206 + if (h2c_len >= 2 && h2c[0] == 0x00 && h2c[1] == 0x00) {
2207 + kfree(h2c);
2208 + rtw89_fw_free_all_early_h2c(rtwdev);
2209 + goto out;
2210 + }
2211 +
2212 + early_h2c = kmalloc(sizeof(*early_h2c), GFP_KERNEL);
2213 + if (!early_h2c) {
2214 + kfree(h2c);
2215 + return -EFAULT;
2216 + }
2217 +
2218 + early_h2c->h2c = h2c;
2219 + early_h2c->h2c_len = h2c_len;
2220 +
2221 + mutex_lock(&rtwdev->mutex);
2222 + list_add_tail(&early_h2c->list, &rtwdev->early_h2c_list);
2223 + mutex_unlock(&rtwdev->mutex);
2224 +
2225 +out:
2226 + return count;
2227 +}
2228 +
2229 +static int rtw89_debug_priv_btc_info_get(struct seq_file *m, void *v)
2230 +{
2231 + struct rtw89_debugfs_priv *debugfs_priv = m->private;
2232 + struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2233 +
2234 + rtw89_btc_dump_info(rtwdev, m);
2235 +
2236 + return 0;
2237 +}
2238 +
2239 +static ssize_t rtw89_debug_priv_btc_manual_set(struct file *filp,
2240 + const char __user *user_buf,
2241 + size_t count, loff_t *loff)
2242 +{
2243 + struct rtw89_debugfs_priv *debugfs_priv = filp->private_data;
2244 + struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2245 + struct rtw89_btc *btc = &rtwdev->btc;
2246 + bool btc_manual;
2247 +
2248 + if (kstrtobool_from_user(user_buf, count, &btc_manual))
2249 + goto out;
2250 +
2251 + btc->ctrl.manual = btc_manual;
2252 +out:
2253 + return count;
2254 +}
2255 +
2256 +static ssize_t rtw89_debug_fw_log_btc_manual_set(struct file *filp,
2257 + const char __user *user_buf,
2258 + size_t count, loff_t *loff)
2259 +{
2260 + struct rtw89_debugfs_priv *debugfs_priv = filp->private_data;
2261 + struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2262 + struct rtw89_fw_info *fw_info = &rtwdev->fw;
2263 + bool fw_log_manual;
2264 +
2265 + if (kstrtobool_from_user(user_buf, count, &fw_log_manual))
2266 + goto out;
2267 +
2268 + mutex_lock(&rtwdev->mutex);
2269 + fw_info->fw_log_enable = fw_log_manual;
2270 + rtw89_fw_h2c_fw_log(rtwdev, fw_log_manual);
2271 + mutex_unlock(&rtwdev->mutex);
2272 +out:
2273 + return count;
2274 +}
2275 +
2276 +static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta)
2277 +{
2278 + static const char * const he_gi_str[] = {
2279 + [NL80211_RATE_INFO_HE_GI_0_8] = "0.8",
2280 + [NL80211_RATE_INFO_HE_GI_1_6] = "1.6",
2281 + [NL80211_RATE_INFO_HE_GI_3_2] = "3.2",
2282 + };
2283 + struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
2284 + struct rate_info *rate = &rtwsta->ra_report.txrate;
2285 + struct ieee80211_rx_status *status = &rtwsta->rx_status;
2286 + struct seq_file *m = (struct seq_file *)data;
2287 + u8 rssi;
2288 +
2289 + seq_printf(m, "TX rate [%d]: ", rtwsta->mac_id);
2290 +
2291 + if (rate->flags & RATE_INFO_FLAGS_MCS)
2292 + seq_printf(m, "HT MCS-%d%s", rate->mcs,
2293 + rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : "");
2294 + else if (rate->flags & RATE_INFO_FLAGS_VHT_MCS)
2295 + seq_printf(m, "VHT %dSS MCS-%d%s", rate->nss, rate->mcs,
2296 + rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : "");
2297 + else if (rate->flags & RATE_INFO_FLAGS_HE_MCS)
2298 + seq_printf(m, "HE %dSS MCS-%d GI:%s", rate->nss, rate->mcs,
2299 + rate->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ?
2300 + he_gi_str[rate->he_gi] : "N/A");
2301 + else
2302 + seq_printf(m, "Legacy %d", rate->legacy);
2303 + seq_printf(m, "\t(hw_rate=0x%x)", rtwsta->ra_report.hw_rate);
2304 + seq_printf(m, "\t==> agg_wait=%d (%d)\n", rtwsta->max_agg_wait,
2305 + sta->max_rc_amsdu_len);
2306 +
2307 + seq_printf(m, "RX rate [%d]: ", rtwsta->mac_id);
2308 +
2309 + switch (status->encoding) {
2310 + case RX_ENC_LEGACY:
2311 + seq_printf(m, "Legacy %d", status->rate_idx +
2312 + (status->band == NL80211_BAND_5GHZ ? 4 : 0));
2313 + break;
2314 + case RX_ENC_HT:
2315 + seq_printf(m, "HT MCS-%d%s", status->rate_idx,
2316 + status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : "");
2317 + break;
2318 + case RX_ENC_VHT:
2319 + seq_printf(m, "VHT %dSS MCS-%d%s", status->nss, status->rate_idx,
2320 + status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : "");
2321 + break;
2322 + case RX_ENC_HE:
2323 + seq_printf(m, "HE %dSS MCS-%d GI:%s", status->nss, status->rate_idx,
2324 + status->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ?
2325 + he_gi_str[rate->he_gi] : "N/A");
2326 + break;
2327 + }
2328 + seq_printf(m, "\t(hw_rate=0x%x)\n", rtwsta->rx_hw_rate);
2329 +
2330 + rssi = ewma_rssi_read(&rtwsta->avg_rssi);
2331 + seq_printf(m, "RSSI: %d dBm (raw=%d, prev=%d)\n",
2332 + RTW89_RSSI_RAW_TO_DBM(rssi), rssi, rtwsta->prev_rssi);
2333 +}
2334 +
2335 +static void
2336 +rtw89_debug_append_rx_rate(struct seq_file *m, struct rtw89_pkt_stat *pkt_stat,
2337 + enum rtw89_hw_rate first_rate, int len)
2338 +{
2339 + int i;
2340 +
2341 + for (i = 0; i < len; i++)
2342 + seq_printf(m, "%s%u", i == 0 ? "" : ", ",
2343 + pkt_stat->rx_rate_cnt[first_rate + i]);
2344 +}
2345 +
2346 +static const struct rtw89_rx_rate_cnt_info {
2347 + enum rtw89_hw_rate first_rate;
2348 + int len;
2349 + const char *rate_mode;
2350 +} rtw89_rx_rate_cnt_infos[] = {
2351 + {RTW89_HW_RATE_CCK1, 4, "Legacy:"},
2352 + {RTW89_HW_RATE_OFDM6, 8, "OFDM:"},
2353 + {RTW89_HW_RATE_MCS0, 8, "HT 0:"},
2354 + {RTW89_HW_RATE_MCS8, 8, "HT 1:"},
2355 + {RTW89_HW_RATE_VHT_NSS1_MCS0, 10, "VHT 1SS:"},
2356 + {RTW89_HW_RATE_VHT_NSS2_MCS0, 10, "VHT 2SS:"},
2357 + {RTW89_HW_RATE_HE_NSS1_MCS0, 12, "HE 1SS:"},
2358 + {RTW89_HW_RATE_HE_NSS2_MCS0, 12, "HE 2ss:"},
2359 +};
2360 +
2361 +static int rtw89_debug_priv_phy_info_get(struct seq_file *m, void *v)
2362 +{
2363 + struct rtw89_debugfs_priv *debugfs_priv = m->private;
2364 + struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2365 + struct rtw89_traffic_stats *stats = &rtwdev->stats;
2366 + struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat;
2367 + const struct rtw89_rx_rate_cnt_info *info;
2368 + int i;
2369 +
2370 + seq_printf(m, "TP TX: %u [%u] Mbps (lv: %d), RX: %u [%u] Mbps (lv: %d)\n",
2371 + stats->tx_throughput, stats->tx_throughput_raw, stats->tx_tfc_lv,
2372 + stats->rx_throughput, stats->rx_throughput_raw, stats->rx_tfc_lv);
2373 + seq_printf(m, "Beacon: %u\n", pkt_stat->beacon_nr);
2374 + seq_printf(m, "Avg packet length: TX=%u, RX=%u\n", stats->tx_avg_len,
2375 + stats->rx_avg_len);
2376 +
2377 + seq_puts(m, "RX count:\n");
2378 + for (i = 0; i < ARRAY_SIZE(rtw89_rx_rate_cnt_infos); i++) {
2379 + info = &rtw89_rx_rate_cnt_infos[i];
2380 + seq_printf(m, "%10s [", info->rate_mode);
2381 + rtw89_debug_append_rx_rate(m, pkt_stat,
2382 + info->first_rate, info->len);
2383 + seq_puts(m, "]\n");
2384 + }
2385 +
2386 + ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, m);
2387 +
2388 + return 0;
2389 +}
2390 +
2391 +static struct rtw89_debugfs_priv rtw89_debug_priv_read_reg = {
2392 + .cb_read = rtw89_debug_priv_read_reg_get,
2393 + .cb_write = rtw89_debug_priv_read_reg_select,
2394 +};
2395 +
2396 +static struct rtw89_debugfs_priv rtw89_debug_priv_write_reg = {
2397 + .cb_write = rtw89_debug_priv_write_reg_set,
2398 +};
2399 +
2400 +static struct rtw89_debugfs_priv rtw89_debug_priv_read_rf = {
2401 + .cb_read = rtw89_debug_priv_read_rf_get,
2402 + .cb_write = rtw89_debug_priv_read_rf_select,
2403 +};
2404 +
2405 +static struct rtw89_debugfs_priv rtw89_debug_priv_write_rf = {
2406 + .cb_write = rtw89_debug_priv_write_rf_set,
2407 +};
2408 +
2409 +static struct rtw89_debugfs_priv rtw89_debug_priv_rf_reg_dump = {
2410 + .cb_read = rtw89_debug_priv_rf_reg_dump_get,
2411 +};
2412 +
2413 +static struct rtw89_debugfs_priv rtw89_debug_priv_txpwr_table = {
2414 + .cb_read = rtw89_debug_priv_txpwr_table_get,
2415 +};
2416 +
2417 +static struct rtw89_debugfs_priv rtw89_debug_priv_mac_reg_dump = {
2418 + .cb_read = rtw89_debug_priv_mac_reg_dump_get,
2419 + .cb_write = rtw89_debug_priv_mac_reg_dump_select,
2420 +};
2421 +
2422 +static struct rtw89_debugfs_priv rtw89_debug_priv_mac_mem_dump = {
2423 + .cb_read = rtw89_debug_priv_mac_mem_dump_get,
2424 + .cb_write = rtw89_debug_priv_mac_mem_dump_select,
2425 +};
2426 +
2427 +static struct rtw89_debugfs_priv rtw89_debug_priv_mac_dbg_port_dump = {
2428 + .cb_read = rtw89_debug_priv_mac_dbg_port_dump_get,
2429 + .cb_write = rtw89_debug_priv_mac_dbg_port_dump_select,
2430 +};
2431 +
2432 +static struct rtw89_debugfs_priv rtw89_debug_priv_send_h2c = {
2433 + .cb_write = rtw89_debug_priv_send_h2c_set,
2434 +};
2435 +
2436 +static struct rtw89_debugfs_priv rtw89_debug_priv_early_h2c = {
2437 + .cb_read = rtw89_debug_priv_early_h2c_get,
2438 + .cb_write = rtw89_debug_priv_early_h2c_set,
2439 +};
2440 +
2441 +static struct rtw89_debugfs_priv rtw89_debug_priv_btc_info = {
2442 + .cb_read = rtw89_debug_priv_btc_info_get,
2443 +};
2444 +
2445 +static struct rtw89_debugfs_priv rtw89_debug_priv_btc_manual = {
2446 + .cb_write = rtw89_debug_priv_btc_manual_set,
2447 +};
2448 +
2449 +static struct rtw89_debugfs_priv rtw89_debug_priv_fw_log_manual = {
2450 + .cb_write = rtw89_debug_fw_log_btc_manual_set,
2451 +};
2452 +
2453 +static struct rtw89_debugfs_priv rtw89_debug_priv_phy_info = {
2454 + .cb_read = rtw89_debug_priv_phy_info_get,
2455 +};
2456 +
2457 +#define rtw89_debugfs_add(name, mode, fopname, parent) \
2458 + do { \
2459 + rtw89_debug_priv_ ##name.rtwdev = rtwdev; \
2460 + if (!debugfs_create_file(#name, mode, \
2461 + parent, &rtw89_debug_priv_ ##name, \
2462 + &file_ops_ ##fopname)) \
2463 + pr_debug("Unable to initialize debugfs:%s\n", #name); \
2464 + } while (0)
2465 +
2466 +#define rtw89_debugfs_add_w(name) \
2467 + rtw89_debugfs_add(name, S_IFREG | 0222, single_w, debugfs_topdir)
2468 +#define rtw89_debugfs_add_rw(name) \
2469 + rtw89_debugfs_add(name, S_IFREG | 0666, common_rw, debugfs_topdir)
2470 +#define rtw89_debugfs_add_r(name) \
2471 + rtw89_debugfs_add(name, S_IFREG | 0444, single_r, debugfs_topdir)
2472 +
2473 +void rtw89_debugfs_init(struct rtw89_dev *rtwdev)
2474 +{
2475 + struct dentry *debugfs_topdir;
2476 +
2477 + debugfs_topdir = debugfs_create_dir("rtw89",
2478 + rtwdev->hw->wiphy->debugfsdir);
2479 +
2480 + rtw89_debugfs_add_rw(read_reg);
2481 + rtw89_debugfs_add_w(write_reg);
2482 + rtw89_debugfs_add_rw(read_rf);
2483 + rtw89_debugfs_add_w(write_rf);
2484 + rtw89_debugfs_add_r(rf_reg_dump);
2485 + rtw89_debugfs_add_r(txpwr_table);
2486 + rtw89_debugfs_add_rw(mac_reg_dump);
2487 + rtw89_debugfs_add_rw(mac_mem_dump);
2488 + rtw89_debugfs_add_rw(mac_dbg_port_dump);
2489 + rtw89_debugfs_add_w(send_h2c);
2490 + rtw89_debugfs_add_rw(early_h2c);
2491 + rtw89_debugfs_add_r(btc_info);
2492 + rtw89_debugfs_add_w(btc_manual);
2493 + rtw89_debugfs_add_w(fw_log_manual);
2494 + rtw89_debugfs_add_r(phy_info);
2495 +}
2496 +#endif
2497 +
2498 +#ifdef CONFIG_RTW89_DEBUGMSG
2499 +void __rtw89_debug(struct rtw89_dev *rtwdev,
2500 + enum rtw89_debug_mask mask,
2501 + const char *fmt, ...)
2502 +{
2503 + struct va_format vaf = {
2504 + .fmt = fmt,
2505 + };
2506 +
2507 + va_list args;
2508 +
2509 + va_start(args, fmt);
2510 + vaf.va = &args;
2511 +
2512 + if (rtw89_debug_mask & mask)
2513 + dev_printk(KERN_DEBUG, rtwdev->dev, "%pV", &vaf);
2514 +
2515 + va_end(args);
2516 +}
2517 +EXPORT_SYMBOL(__rtw89_debug);
2518 +#endif
2519 diff --git a/drivers/net/wireless/realtek/rtw89/debug.h b/drivers/net/wireless/realtek/rtw89/debug.h
2520 new file mode 100644
2521 index 000000000000..f14b726c1a9f
2522 --- /dev/null
2523 +++ b/drivers/net/wireless/realtek/rtw89/debug.h
2524 @@ -0,0 +1,77 @@
2525 +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2526 +/* Copyright(c) 2019-2020 Realtek Corporation
2527 + */
2528 +
2529 +#ifndef __RTW89_DEBUG_H__
2530 +#define __RTW89_DEBUG_H__
2531 +
2532 +#include "core.h"
2533 +
2534 +enum rtw89_debug_mask {
2535 + RTW89_DBG_TXRX = BIT(0),
2536 + RTW89_DBG_RFK = BIT(1),
2537 + RTW89_DBG_RFK_TRACK = BIT(2),
2538 + RTW89_DBG_CFO = BIT(3),
2539 + RTW89_DBG_TSSI = BIT(4),
2540 + RTW89_DBG_TXPWR = BIT(5),
2541 + RTW89_DBG_HCI = BIT(6),
2542 + RTW89_DBG_RA = BIT(7),
2543 + RTW89_DBG_REGD = BIT(8),
2544 + RTW89_DBG_PHY_TRACK = BIT(9),
2545 + RTW89_DBG_DIG = BIT(10),
2546 + RTW89_DBG_SER = BIT(11),
2547 + RTW89_DBG_FW = BIT(12),
2548 + RTW89_DBG_BTC = BIT(13),
2549 + RTW89_DBG_BF = BIT(14),
2550 +};
2551 +
2552 +enum rtw89_debug_mac_reg_sel {
2553 + RTW89_DBG_SEL_MAC_00,
2554 + RTW89_DBG_SEL_MAC_40,
2555 + RTW89_DBG_SEL_MAC_80,
2556 + RTW89_DBG_SEL_MAC_C0,
2557 + RTW89_DBG_SEL_MAC_E0,
2558 + RTW89_DBG_SEL_BB,
2559 + RTW89_DBG_SEL_IQK,
2560 + RTW89_DBG_SEL_RFC,
2561 +};
2562 +
2563 +#ifdef CONFIG_RTW89_DEBUGFS
2564 +void rtw89_debugfs_init(struct rtw89_dev *rtwdev);
2565 +#else
2566 +static inline void rtw89_debugfs_init(struct rtw89_dev *rtwdev) {}
2567 +#endif
2568 +
2569 +#define rtw89_info(rtwdev, a...) dev_info((rtwdev)->dev, ##a)
2570 +#define rtw89_warn(rtwdev, a...) dev_warn((rtwdev)->dev, ##a)
2571 +#define rtw89_err(rtwdev, a...) dev_err((rtwdev)->dev, ##a)
2572 +
2573 +#ifdef CONFIG_RTW89_DEBUGMSG
2574 +extern unsigned int rtw89_debug_mask;
2575 +#define rtw89_debug(rtwdev, a...) __rtw89_debug(rtwdev, ##a)
2576 +
2577 +__printf(3, 4)
2578 +void __rtw89_debug(struct rtw89_dev *rtwdev,
2579 + enum rtw89_debug_mask mask,
2580 + const char *fmt, ...);
2581 +static inline void rtw89_hex_dump(struct rtw89_dev *rtwdev,
2582 + enum rtw89_debug_mask mask,
2583 + const char *prefix_str,
2584 + const void *buf, size_t len)
2585 +{
2586 + if (!(rtw89_debug_mask & mask))
2587 + return;
2588 +
2589 + print_hex_dump_bytes(prefix_str, DUMP_PREFIX_OFFSET, buf, len);
2590 +}
2591 +#else
2592 +static inline void rtw89_debug(struct rtw89_dev *rtwdev,
2593 + enum rtw89_debug_mask mask,
2594 + const char *fmt, ...) {}
2595 +static inline void rtw89_hex_dump(struct rtw89_dev *rtwdev,
2596 + enum rtw89_debug_mask mask,
2597 + const char *prefix_str,
2598 + const void *buf, size_t len) {}
2599 +#endif
2600 +
2601 +#endif
2602 --
2603 2.33.0
2604
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