current/SOURCES/0202-radeon-llvm-Cleanup-makefile.patch

From cebbdd4ac23725963207bf6f8fc7101150e6065f Mon Sep 17 00:00:00 2001
From: Tom Stellard <thomas.stellard@amd.com>
Date: Wed, 29 Aug 2012 13:01:15 +0000
Subject: [PATCH] radeon/llvm: Cleanup makefile

Hopefully, this will fix all the parallel make problems people have
been having.
---
 src/gallium/drivers/radeon/Makefile         | 24 +++++++++++-------------
 src/gallium/drivers/radeon/Makefile.sources | 26 ++++++++++++++++++++++++++
 2 files changed, 37 insertions(+), 13 deletions(-)

diff --git a/src/gallium/drivers/radeon/Makefile b/src/gallium/drivers/radeon/Makefile
index 43f668a..7f1c613 100644
--- a/src/gallium/drivers/radeon/Makefile
+++ b/src/gallium/drivers/radeon/Makefile
@@ -20,8 +20,6 @@ tablegen = $(TBLGEN) -I $(LLVM_INCLUDEDIR) $1 $2 -o $3
 
 HAVE_LLVM_INTRINSICS = $(shell grep IntrinsicsR600.td $(LLVM_INCLUDEDIR)/llvm/Intrinsics.td)
 
-gen: $(GENERATED_SOURCES)
-
 SIRegisterInfo.td: SIGenRegisterInfo.pl
        $(PERL) $^ > $@
 
@@ -38,37 +36,37 @@ endif
 R600RegisterInfo.td: R600GenRegisterInfo.pl
        $(PERL) $^ > $@
 
-AMDGPUGenRegisterInfo.inc: *.td
+AMDGPUGenRegisterInfo.inc: $(TD_FILES)
        $(call tablegen, -gen-register-info, AMDGPU.td, $@)
 
-AMDGPUGenInstrInfo.inc: *.td
+AMDGPUGenInstrInfo.inc: $(TD_FILES)
        $(call tablegen, -gen-instr-info, AMDGPU.td, $@)
 
-AMDGPUGenAsmWriter.inc: *.td
+AMDGPUGenAsmWriter.inc: $(TD_FILES)
        $(call tablegen, -gen-asm-writer, AMDGPU.td, $@)
 
-AMDGPUGenDAGISel.inc: *.td
+AMDGPUGenDAGISel.inc: $(TD_FILES)
        $(call tablegen, -gen-dag-isel, AMDGPU.td, $@)
 
-AMDGPUGenCallingConv.inc: *.td
+AMDGPUGenCallingConv.inc: $(TD_FILES)
        $(call tablegen, -gen-callingconv, AMDGPU.td, $@)
 
-AMDGPUGenSubtargetInfo.inc: *.td
+AMDGPUGenSubtargetInfo.inc: $(TD_FILES)
        $(call tablegen, -gen-subtarget, AMDGPU.td, $@)
 
-AMDGPUGenEDInfo.inc: *.td
+AMDGPUGenEDInfo.inc: $(TD_FILES)
        $(call tablegen, -gen-enhanced-disassembly-info, AMDGPU.td, $@)
 
-AMDGPUGenIntrinsics.inc: *.td
+AMDGPUGenIntrinsics.inc: $(TD_FILES)
        $(call tablegen, -gen-tgt-intrinsic, AMDGPU.td, $@)
 
-AMDGPUGenCodeEmitter.inc: *.td
+AMDGPUGenCodeEmitter.inc: $(TD_FILES)
        $(call tablegen, -gen-emitter, AMDGPU.td, $@)
 
-AMDGPUGenMCCodeEmitter.inc: *.td
+AMDGPUGenMCCodeEmitter.inc: $(TD_FILES)
        $(call tablegen, -mc-emitter -gen-emitter, AMDGPU.td, $@)
 
-AMDGPUGenDFAPacketizer.inc: *.td
+AMDGPUGenDFAPacketizer.inc: $(TD_FILES)
        $(call tablegen, -gen-dfa-packetizer, AMDGPU.td, $@)
 
 LOADER_LIBS=$(shell llvm-config --libs bitreader asmparser)
diff --git a/src/gallium/drivers/radeon/Makefile.sources b/src/gallium/drivers/radeon/Makefile.sources
index 2eb1120..333dd03 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -1,4 +1,30 @@
 
+TD_FILES := \
+       AMDGPU.td               \
+       AMDGPUInstrInfo.td      \
+       AMDGPUInstructions.td   \
+       AMDGPUIntrinsics.td     \
+       AMDGPURegisterInfo.td   \
+       AMDILBase.td            \
+       AMDILInstrInfo.td       \
+       AMDILIntrinsics.td      \
+       AMDILRegisterInfo.td    \
+       Processors.td           \
+       R600InstrInfo.td        \
+       R600Instructions.td     \
+       R600Intrinsics.td       \
+       R600IntrinsicsNoOpenCL.td       \
+       R600IntrinsicsOpenCL.td \
+       R600RegisterInfo.td     \
+       R600Schedule.td         \
+       SIInstrFormats.td       \
+       SIInstrInfo.td          \
+       SIInstructions.td       \
+       SIIntrinsics.td         \
+       SIRegisterInfo.td       \
+       SISchedule.td
+
+
 GENERATED_SOURCES := \
        R600Intrinsics.td               \
        R600RegisterInfo.td             \
-- 
1.7.12

1	From cebbdd4ac23725963207bf6f8fc7101150e6065f Mon Sep 17 00:00:00 2001
2	From: Tom Stellard <thomas.stellard@amd.com>
3	Date: Wed, 29 Aug 2012 13:01:15 +0000
4	Subject: [PATCH] radeon/llvm: Cleanup makefile
5
6	Hopefully, this will fix all the parallel make problems people have
7	been having.
8	---
9	src/gallium/drivers/radeon/Makefile \| 24 +++++++++++-------------
10	src/gallium/drivers/radeon/Makefile.sources \| 26 ++++++++++++++++++++++++++
11	2 files changed, 37 insertions(+), 13 deletions(-)
12
13	diff --git a/src/gallium/drivers/radeon/Makefile b/src/gallium/drivers/radeon/Makefile
14	index 43f668a..7f1c613 100644
15	--- a/src/gallium/drivers/radeon/Makefile
16	+++ b/src/gallium/drivers/radeon/Makefile
17	@@ -20,8 +20,6 @@ tablegen = $(TBLGEN) -I $(LLVM_INCLUDEDIR) $1 $2 -o $3
18
19	HAVE_LLVM_INTRINSICS = $(shell grep IntrinsicsR600.td $(LLVM_INCLUDEDIR)/llvm/Intrinsics.td)
20
21	-gen: $(GENERATED_SOURCES)
22	-
23	SIRegisterInfo.td: SIGenRegisterInfo.pl
24	$(PERL) $^ > $@
25
26	@@ -38,37 +36,37 @@ endif
27	R600RegisterInfo.td: R600GenRegisterInfo.pl
28	$(PERL) $^ > $@
29
30	-AMDGPUGenRegisterInfo.inc: *.td
31	+AMDGPUGenRegisterInfo.inc: $(TD_FILES)
32	$(call tablegen, -gen-register-info, AMDGPU.td, $@)
33
34	-AMDGPUGenInstrInfo.inc: *.td
35	+AMDGPUGenInstrInfo.inc: $(TD_FILES)
36	$(call tablegen, -gen-instr-info, AMDGPU.td, $@)
37
38	-AMDGPUGenAsmWriter.inc: *.td
39	+AMDGPUGenAsmWriter.inc: $(TD_FILES)
40	$(call tablegen, -gen-asm-writer, AMDGPU.td, $@)
41
42	-AMDGPUGenDAGISel.inc: *.td
43	+AMDGPUGenDAGISel.inc: $(TD_FILES)
44	$(call tablegen, -gen-dag-isel, AMDGPU.td, $@)
45
46	-AMDGPUGenCallingConv.inc: *.td
47	+AMDGPUGenCallingConv.inc: $(TD_FILES)
48	$(call tablegen, -gen-callingconv, AMDGPU.td, $@)
49
50	-AMDGPUGenSubtargetInfo.inc: *.td
51	+AMDGPUGenSubtargetInfo.inc: $(TD_FILES)
52	$(call tablegen, -gen-subtarget, AMDGPU.td, $@)
53
54	-AMDGPUGenEDInfo.inc: *.td
55	+AMDGPUGenEDInfo.inc: $(TD_FILES)
56	$(call tablegen, -gen-enhanced-disassembly-info, AMDGPU.td, $@)
57
58	-AMDGPUGenIntrinsics.inc: *.td
59	+AMDGPUGenIntrinsics.inc: $(TD_FILES)
60	$(call tablegen, -gen-tgt-intrinsic, AMDGPU.td, $@)
61
62	-AMDGPUGenCodeEmitter.inc: *.td
63	+AMDGPUGenCodeEmitter.inc: $(TD_FILES)
64	$(call tablegen, -gen-emitter, AMDGPU.td, $@)
65
66	-AMDGPUGenMCCodeEmitter.inc: *.td
67	+AMDGPUGenMCCodeEmitter.inc: $(TD_FILES)
68	$(call tablegen, -mc-emitter -gen-emitter, AMDGPU.td, $@)
69
70	-AMDGPUGenDFAPacketizer.inc: *.td
71	+AMDGPUGenDFAPacketizer.inc: $(TD_FILES)
72	$(call tablegen, -gen-dfa-packetizer, AMDGPU.td, $@)
73
74	LOADER_LIBS=$(shell llvm-config --libs bitreader asmparser)
75	diff --git a/src/gallium/drivers/radeon/Makefile.sources b/src/gallium/drivers/radeon/Makefile.sources
76	index 2eb1120..333dd03 100644
77	--- a/src/gallium/drivers/radeon/Makefile.sources
78	+++ b/src/gallium/drivers/radeon/Makefile.sources
79	@@ -1,4 +1,30 @@
80
81	+TD_FILES := \
82	+ AMDGPU.td \
83	+ AMDGPUInstrInfo.td \
84	+ AMDGPUInstructions.td \
85	+ AMDGPUIntrinsics.td \
86	+ AMDGPURegisterInfo.td \
87	+ AMDILBase.td \
88	+ AMDILInstrInfo.td \
89	+ AMDILIntrinsics.td \
90	+ AMDILRegisterInfo.td \
91	+ Processors.td \
92	+ R600InstrInfo.td \
93	+ R600Instructions.td \
94	+ R600Intrinsics.td \
95	+ R600IntrinsicsNoOpenCL.td \
96	+ R600IntrinsicsOpenCL.td \
97	+ R600RegisterInfo.td \
98	+ R600Schedule.td \
99	+ SIInstrFormats.td \
100	+ SIInstrInfo.td \
101	+ SIInstructions.td \
102	+ SIIntrinsics.td \
103	+ SIRegisterInfo.td \
104	+ SISchedule.td
105	+
106	+
107	GENERATED_SOURCES := \
108	R600Intrinsics.td \
109	R600RegisterInfo.td \
110	--
111	1.7.12
112