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From foo@baz Tue Mar 8 08:32:37 PM CET 2022 |
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From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk> |
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Date: Fri, 11 Feb 2022 16:45:54 +0000 |
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Subject: ARM: report Spectre v2 status through sysfs |
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|
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From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk> |
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|
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commit 9dd78194a3722fa6712192cdd4f7032d45112a9a upstream. |
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|
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As per other architectures, add support for reporting the Spectre |
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vulnerability status via sysfs CPU. |
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|
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Acked-by: Catalin Marinas <catalin.marinas@arm.com> |
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Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> |
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Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
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--- |
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arch/arm/include/asm/spectre.h | 28 ++++++++ |
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arch/arm/kernel/Makefile | 2 |
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arch/arm/kernel/spectre.c | 54 +++++++++++++++ |
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arch/arm/mm/Kconfig | 1 |
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arch/arm/mm/proc-v7-bugs.c | 141 +++++++++++++++++++++++++++++------------ |
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5 files changed, 187 insertions(+), 39 deletions(-) |
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create mode 100644 arch/arm/include/asm/spectre.h |
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create mode 100644 arch/arm/kernel/spectre.c |
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|
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--- /dev/null |
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+++ b/arch/arm/include/asm/spectre.h |
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@@ -0,0 +1,28 @@ |
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+/* SPDX-License-Identifier: GPL-2.0-only */ |
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+ |
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+#ifndef __ASM_SPECTRE_H |
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+#define __ASM_SPECTRE_H |
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+ |
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+enum { |
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+ SPECTRE_UNAFFECTED, |
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+ SPECTRE_MITIGATED, |
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+ SPECTRE_VULNERABLE, |
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+}; |
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+ |
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+enum { |
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+ __SPECTRE_V2_METHOD_BPIALL, |
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+ __SPECTRE_V2_METHOD_ICIALLU, |
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+ __SPECTRE_V2_METHOD_SMC, |
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+ __SPECTRE_V2_METHOD_HVC, |
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+}; |
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+ |
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+enum { |
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+ SPECTRE_V2_METHOD_BPIALL = BIT(__SPECTRE_V2_METHOD_BPIALL), |
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+ SPECTRE_V2_METHOD_ICIALLU = BIT(__SPECTRE_V2_METHOD_ICIALLU), |
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+ SPECTRE_V2_METHOD_SMC = BIT(__SPECTRE_V2_METHOD_SMC), |
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+ SPECTRE_V2_METHOD_HVC = BIT(__SPECTRE_V2_METHOD_HVC), |
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+}; |
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+ |
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+void spectre_v2_update_state(unsigned int state, unsigned int methods); |
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+ |
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+#endif |
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--- a/arch/arm/kernel/Makefile |
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+++ b/arch/arm/kernel/Makefile |
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@@ -106,4 +106,6 @@ endif |
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|
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obj-$(CONFIG_HAVE_ARM_SMCCC) += smccc-call.o |
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|
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+obj-$(CONFIG_GENERIC_CPU_VULNERABILITIES) += spectre.o |
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+ |
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extra-y := $(head-y) vmlinux.lds |
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--- /dev/null |
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+++ b/arch/arm/kernel/spectre.c |
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@@ -0,0 +1,54 @@ |
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+// SPDX-License-Identifier: GPL-2.0-only |
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+#include <linux/cpu.h> |
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+#include <linux/device.h> |
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+ |
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+#include <asm/spectre.h> |
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+ |
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+ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, |
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+ char *buf) |
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+{ |
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+ return sprintf(buf, "Mitigation: __user pointer sanitization\n"); |
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+} |
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+ |
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+static unsigned int spectre_v2_state; |
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+static unsigned int spectre_v2_methods; |
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+ |
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+void spectre_v2_update_state(unsigned int state, unsigned int method) |
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+{ |
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+ if (state > spectre_v2_state) |
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+ spectre_v2_state = state; |
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+ spectre_v2_methods |= method; |
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+} |
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+ |
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+ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, |
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+ char *buf) |
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+{ |
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+ const char *method; |
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+ |
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+ if (spectre_v2_state == SPECTRE_UNAFFECTED) |
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+ return sprintf(buf, "%s\n", "Not affected"); |
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+ |
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+ if (spectre_v2_state != SPECTRE_MITIGATED) |
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+ return sprintf(buf, "%s\n", "Vulnerable"); |
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+ |
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+ switch (spectre_v2_methods) { |
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+ case SPECTRE_V2_METHOD_BPIALL: |
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+ method = "Branch predictor hardening"; |
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+ break; |
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+ |
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+ case SPECTRE_V2_METHOD_ICIALLU: |
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+ method = "I-cache invalidation"; |
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+ break; |
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+ |
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+ case SPECTRE_V2_METHOD_SMC: |
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+ case SPECTRE_V2_METHOD_HVC: |
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+ method = "Firmware call"; |
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+ break; |
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+ |
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+ default: |
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+ method = "Multiple mitigations"; |
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+ break; |
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+ } |
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+ |
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+ return sprintf(buf, "Mitigation: %s\n", method); |
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+} |
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--- a/arch/arm/mm/Kconfig |
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+++ b/arch/arm/mm/Kconfig |
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@@ -830,6 +830,7 @@ config CPU_BPREDICT_DISABLE |
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|
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config CPU_SPECTRE |
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bool |
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+ select GENERIC_CPU_VULNERABILITIES |
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|
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config HARDEN_BRANCH_PREDICTOR |
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bool "Harden the branch predictor against aliasing attacks" if EXPERT |
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--- a/arch/arm/mm/proc-v7-bugs.c |
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+++ b/arch/arm/mm/proc-v7-bugs.c |
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@@ -6,8 +6,35 @@ |
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#include <asm/cp15.h> |
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#include <asm/cputype.h> |
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#include <asm/proc-fns.h> |
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+#include <asm/spectre.h> |
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#include <asm/system_misc.h> |
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|
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+#ifdef CONFIG_ARM_PSCI |
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+static int __maybe_unused spectre_v2_get_cpu_fw_mitigation_state(void) |
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+{ |
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+ struct arm_smccc_res res; |
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+ |
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+ arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, |
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+ ARM_SMCCC_ARCH_WORKAROUND_1, &res); |
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+ |
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+ switch ((int)res.a0) { |
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+ case SMCCC_RET_SUCCESS: |
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+ return SPECTRE_MITIGATED; |
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+ |
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+ case SMCCC_ARCH_WORKAROUND_RET_UNAFFECTED: |
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+ return SPECTRE_UNAFFECTED; |
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+ |
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+ default: |
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+ return SPECTRE_VULNERABLE; |
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+ } |
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+} |
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+#else |
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+static int __maybe_unused spectre_v2_get_cpu_fw_mitigation_state(void) |
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+{ |
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+ return SPECTRE_VULNERABLE; |
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+} |
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+#endif |
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+ |
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#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR |
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DEFINE_PER_CPU(harden_branch_predictor_fn_t, harden_branch_predictor_fn); |
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|
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@@ -36,13 +63,60 @@ static void __maybe_unused call_hvc_arch |
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arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL); |
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} |
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|
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-static void cpu_v7_spectre_init(void) |
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+static unsigned int spectre_v2_install_workaround(unsigned int method) |
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{ |
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const char *spectre_v2_method = NULL; |
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int cpu = smp_processor_id(); |
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|
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if (per_cpu(harden_branch_predictor_fn, cpu)) |
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- return; |
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+ return SPECTRE_MITIGATED; |
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+ |
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+ switch (method) { |
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+ case SPECTRE_V2_METHOD_BPIALL: |
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+ per_cpu(harden_branch_predictor_fn, cpu) = |
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+ harden_branch_predictor_bpiall; |
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+ spectre_v2_method = "BPIALL"; |
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+ break; |
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+ |
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+ case SPECTRE_V2_METHOD_ICIALLU: |
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+ per_cpu(harden_branch_predictor_fn, cpu) = |
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+ harden_branch_predictor_iciallu; |
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+ spectre_v2_method = "ICIALLU"; |
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+ break; |
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+ |
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+ case SPECTRE_V2_METHOD_HVC: |
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+ per_cpu(harden_branch_predictor_fn, cpu) = |
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+ call_hvc_arch_workaround_1; |
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+ cpu_do_switch_mm = cpu_v7_hvc_switch_mm; |
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+ spectre_v2_method = "hypervisor"; |
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+ break; |
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+ |
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+ case SPECTRE_V2_METHOD_SMC: |
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+ per_cpu(harden_branch_predictor_fn, cpu) = |
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+ call_smc_arch_workaround_1; |
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+ cpu_do_switch_mm = cpu_v7_smc_switch_mm; |
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+ spectre_v2_method = "firmware"; |
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+ break; |
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+ } |
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+ |
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+ if (spectre_v2_method) |
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+ pr_info("CPU%u: Spectre v2: using %s workaround\n", |
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+ smp_processor_id(), spectre_v2_method); |
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+ |
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+ return SPECTRE_MITIGATED; |
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+} |
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+#else |
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+static unsigned int spectre_v2_install_workaround(unsigned int method) |
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+{ |
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+ pr_info("CPU%u: Spectre V2: workarounds disabled by configuration\n"); |
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+ |
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+ return SPECTRE_VULNERABLE; |
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+} |
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+#endif |
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+ |
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+static void cpu_v7_spectre_v2_init(void) |
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+{ |
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+ unsigned int state, method = 0; |
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|
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switch (read_cpuid_part()) { |
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case ARM_CPU_PART_CORTEX_A8: |
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@@ -51,68 +125,57 @@ static void cpu_v7_spectre_init(void) |
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case ARM_CPU_PART_CORTEX_A17: |
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case ARM_CPU_PART_CORTEX_A73: |
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case ARM_CPU_PART_CORTEX_A75: |
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- per_cpu(harden_branch_predictor_fn, cpu) = |
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- harden_branch_predictor_bpiall; |
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- spectre_v2_method = "BPIALL"; |
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+ state = SPECTRE_MITIGATED; |
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+ method = SPECTRE_V2_METHOD_BPIALL; |
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break; |
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|
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case ARM_CPU_PART_CORTEX_A15: |
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case ARM_CPU_PART_BRAHMA_B15: |
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- per_cpu(harden_branch_predictor_fn, cpu) = |
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- harden_branch_predictor_iciallu; |
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- spectre_v2_method = "ICIALLU"; |
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+ state = SPECTRE_MITIGATED; |
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+ method = SPECTRE_V2_METHOD_ICIALLU; |
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break; |
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|
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-#ifdef CONFIG_ARM_PSCI |
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case ARM_CPU_PART_BRAHMA_B53: |
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/* Requires no workaround */ |
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+ state = SPECTRE_UNAFFECTED; |
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break; |
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+ |
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default: |
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/* Other ARM CPUs require no workaround */ |
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- if (read_cpuid_implementor() == ARM_CPU_IMP_ARM) |
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+ if (read_cpuid_implementor() == ARM_CPU_IMP_ARM) { |
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+ state = SPECTRE_UNAFFECTED; |
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break; |
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+ } |
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+ |
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fallthrough; |
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- /* Cortex A57/A72 require firmware workaround */ |
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- case ARM_CPU_PART_CORTEX_A57: |
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- case ARM_CPU_PART_CORTEX_A72: { |
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- struct arm_smccc_res res; |
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|
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- arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, |
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- ARM_SMCCC_ARCH_WORKAROUND_1, &res); |
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- if ((int)res.a0 != 0) |
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- return; |
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+ /* Cortex A57/A72 require firmware workaround */ |
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+ case ARM_CPU_PART_CORTEX_A57: |
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+ case ARM_CPU_PART_CORTEX_A72: |
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+ state = spectre_v2_get_cpu_fw_mitigation_state(); |
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+ if (state != SPECTRE_MITIGATED) |
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+ break; |
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|
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switch (arm_smccc_1_1_get_conduit()) { |
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case SMCCC_CONDUIT_HVC: |
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- per_cpu(harden_branch_predictor_fn, cpu) = |
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- call_hvc_arch_workaround_1; |
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- cpu_do_switch_mm = cpu_v7_hvc_switch_mm; |
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- spectre_v2_method = "hypervisor"; |
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+ method = SPECTRE_V2_METHOD_HVC; |
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break; |
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|
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case SMCCC_CONDUIT_SMC: |
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- per_cpu(harden_branch_predictor_fn, cpu) = |
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- call_smc_arch_workaround_1; |
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- cpu_do_switch_mm = cpu_v7_smc_switch_mm; |
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- spectre_v2_method = "firmware"; |
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+ method = SPECTRE_V2_METHOD_SMC; |
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break; |
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|
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default: |
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+ state = SPECTRE_VULNERABLE; |
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break; |
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} |
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} |
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-#endif |
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- } |
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|
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- if (spectre_v2_method) |
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- pr_info("CPU%u: Spectre v2: using %s workaround\n", |
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- smp_processor_id(), spectre_v2_method); |
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-} |
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-#else |
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-static void cpu_v7_spectre_init(void) |
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-{ |
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+ if (state == SPECTRE_MITIGATED) |
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+ state = spectre_v2_install_workaround(method); |
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+ |
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+ spectre_v2_update_state(state, method); |
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} |
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-#endif |
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|
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static __maybe_unused bool cpu_v7_check_auxcr_set(bool *warned, |
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u32 mask, const char *msg) |
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@@ -142,16 +205,16 @@ static bool check_spectre_auxcr(bool *wa |
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void cpu_v7_ca8_ibe(void) |
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{ |
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if (check_spectre_auxcr(this_cpu_ptr(&spectre_warned), BIT(6))) |
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- cpu_v7_spectre_init(); |
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+ cpu_v7_spectre_v2_init(); |
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} |
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|
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void cpu_v7_ca15_ibe(void) |
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{ |
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if (check_spectre_auxcr(this_cpu_ptr(&spectre_warned), BIT(0))) |
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- cpu_v7_spectre_init(); |
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+ cpu_v7_spectre_v2_init(); |
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} |
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|
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void cpu_v7_bugs_init(void) |
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{ |
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- cpu_v7_spectre_init(); |
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+ cpu_v7_spectre_v2_init(); |
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} |
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