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From foo@baz Tue Mar 8 08:47:19 PM CET 2022 |
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From: Joey Gouly <joey.gouly@arm.com> |
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Date: Fri, 10 Dec 2021 16:54:31 +0000 |
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Subject: arm64: add ID_AA64ISAR2_EL1 sys register |
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|
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From: Joey Gouly <joey.gouly@arm.com> |
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|
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commit 9e45365f1469ef2b934f9d035975dbc9ad352116 upstream. |
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|
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This is a new ID register, introduced in 8.7. |
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|
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Signed-off-by: Joey Gouly <joey.gouly@arm.com> |
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Cc: Will Deacon <will@kernel.org> |
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Cc: Marc Zyngier <maz@kernel.org> |
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Cc: James Morse <james.morse@arm.com> |
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Cc: Alexandru Elisei <alexandru.elisei@arm.com> |
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Cc: Suzuki K Poulose <suzuki.poulose@arm.com> |
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Cc: Reiji Watanabe <reijiw@google.com> |
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Acked-by: Marc Zyngier <maz@kernel.org> |
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Link: https://lore.kernel.org/r/20211210165432.8106-3-joey.gouly@arm.com |
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Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> |
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Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
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--- |
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arch/arm64/include/asm/cpu.h | 1 + |
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arch/arm64/include/asm/sysreg.h | 15 +++++++++++++++ |
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arch/arm64/kernel/cpufeature.c | 9 +++++++++ |
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arch/arm64/kernel/cpuinfo.c | 1 + |
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arch/arm64/kvm/sys_regs.c | 2 +- |
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5 files changed, 27 insertions(+), 1 deletion(-) |
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|
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--- a/arch/arm64/include/asm/cpu.h |
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+++ b/arch/arm64/include/asm/cpu.h |
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@@ -51,6 +51,7 @@ struct cpuinfo_arm64 { |
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u64 reg_id_aa64dfr1; |
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u64 reg_id_aa64isar0; |
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u64 reg_id_aa64isar1; |
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+ u64 reg_id_aa64isar2; |
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u64 reg_id_aa64mmfr0; |
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u64 reg_id_aa64mmfr1; |
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u64 reg_id_aa64mmfr2; |
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--- a/arch/arm64/include/asm/sysreg.h |
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+++ b/arch/arm64/include/asm/sysreg.h |
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@@ -180,6 +180,7 @@ |
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|
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#define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) |
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#define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1) |
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+#define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2) |
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|
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#define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) |
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#define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) |
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@@ -764,6 +765,20 @@ |
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#define ID_AA64ISAR1_GPI_NI 0x0 |
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#define ID_AA64ISAR1_GPI_IMP_DEF 0x1 |
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|
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+/* id_aa64isar2 */ |
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+#define ID_AA64ISAR2_RPRES_SHIFT 4 |
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+#define ID_AA64ISAR2_WFXT_SHIFT 0 |
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+ |
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+#define ID_AA64ISAR2_RPRES_8BIT 0x0 |
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+#define ID_AA64ISAR2_RPRES_12BIT 0x1 |
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+/* |
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+ * Value 0x1 has been removed from the architecture, and is |
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+ * reserved, but has not yet been removed from the ARM ARM |
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+ * as of ARM DDI 0487G.b. |
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+ */ |
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+#define ID_AA64ISAR2_WFXT_NI 0x0 |
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+#define ID_AA64ISAR2_WFXT_SUPPORTED 0x2 |
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+ |
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/* id_aa64pfr0 */ |
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#define ID_AA64PFR0_CSV3_SHIFT 60 |
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#define ID_AA64PFR0_CSV2_SHIFT 56 |
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--- a/arch/arm64/kernel/cpufeature.c |
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+++ b/arch/arm64/kernel/cpufeature.c |
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@@ -225,6 +225,10 @@ static const struct arm64_ftr_bits ftr_i |
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ARM64_FTR_END, |
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}; |
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|
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+static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { |
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+ ARM64_FTR_END, |
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+}; |
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+ |
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static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { |
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), |
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), |
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@@ -637,6 +641,7 @@ static const struct __ftr_reg_entry { |
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ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), |
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ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, |
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&id_aa64isar1_override), |
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+ ARM64_FTR_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2), |
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|
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/* Op1 = 0, CRn = 0, CRm = 7 */ |
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ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), |
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@@ -933,6 +938,7 @@ void __init init_cpu_features(struct cpu |
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init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); |
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init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); |
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init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); |
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+ init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); |
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init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); |
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init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); |
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init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); |
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@@ -1151,6 +1157,8 @@ void update_cpu_features(int cpu, |
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info->reg_id_aa64isar0, boot->reg_id_aa64isar0); |
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taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, |
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info->reg_id_aa64isar1, boot->reg_id_aa64isar1); |
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+ taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, |
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+ info->reg_id_aa64isar2, boot->reg_id_aa64isar2); |
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|
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/* |
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* Differing PARange support is fine as long as all peripherals and |
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@@ -1272,6 +1280,7 @@ u64 __read_sysreg_by_encoding(u32 sys_id |
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read_sysreg_case(SYS_ID_AA64MMFR2_EL1); |
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read_sysreg_case(SYS_ID_AA64ISAR0_EL1); |
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read_sysreg_case(SYS_ID_AA64ISAR1_EL1); |
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+ read_sysreg_case(SYS_ID_AA64ISAR2_EL1); |
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|
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read_sysreg_case(SYS_CNTFRQ_EL0); |
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read_sysreg_case(SYS_CTR_EL0); |
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--- a/arch/arm64/kernel/cpuinfo.c |
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+++ b/arch/arm64/kernel/cpuinfo.c |
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@@ -391,6 +391,7 @@ static void __cpuinfo_store_cpu(struct c |
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info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1); |
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info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1); |
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info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1); |
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+ info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1); |
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info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); |
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info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); |
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info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1); |
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--- a/arch/arm64/kvm/sys_regs.c |
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+++ b/arch/arm64/kvm/sys_regs.c |
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@@ -1518,7 +1518,7 @@ static const struct sys_reg_desc sys_reg |
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/* CRm=6 */ |
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ID_SANITISED(ID_AA64ISAR0_EL1), |
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ID_SANITISED(ID_AA64ISAR1_EL1), |
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- ID_UNALLOCATED(6,2), |
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+ ID_SANITISED(ID_AA64ISAR2_EL1), |
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ID_UNALLOCATED(6,3), |
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ID_UNALLOCATED(6,4), |
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ID_UNALLOCATED(6,5), |
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