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From foo@baz Tue Mar 8 08:47:19 PM CET 2022 |
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From: Suzuki K Poulose <suzuki.poulose@arm.com> |
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Date: Tue, 19 Oct 2021 17:31:39 +0100 |
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Subject: arm64: Add Neoverse-N2, Cortex-A710 CPU part definition |
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From: Suzuki K Poulose <suzuki.poulose@arm.com> |
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commit 2d0d656700d67239a57afaf617439143d8dac9be upstream. |
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Add the CPU Partnumbers for the new Arm designs. |
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Cc: Catalin Marinas <catalin.marinas@arm.com> |
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Cc: Mark Rutland <mark.rutland@arm.com> |
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Cc: Will Deacon <will@kernel.org> |
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Acked-by: Catalin Marinas <catalin.marinas@arm.com> |
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Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> |
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Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> |
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Link: https://lore.kernel.org/r/20211019163153.3692640-2-suzuki.poulose@arm.com |
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Signed-off-by: Will Deacon <will@kernel.org> |
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Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
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--- |
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arch/arm64/include/asm/cputype.h | 4 ++++ |
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1 file changed, 4 insertions(+) |
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--- a/arch/arm64/include/asm/cputype.h |
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+++ b/arch/arm64/include/asm/cputype.h |
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@@ -74,6 +74,8 @@ |
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#define ARM_CPU_PART_NEOVERSE_N1 0xD0C |
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#define ARM_CPU_PART_CORTEX_A77 0xD0D |
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#define ARM_CPU_PART_CORTEX_A510 0xD46 |
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+#define ARM_CPU_PART_CORTEX_A710 0xD47 |
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+#define ARM_CPU_PART_NEOVERSE_N2 0xD49 |
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#define APM_CPU_PART_POTENZA 0x000 |
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@@ -115,6 +117,8 @@ |
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#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1) |
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#define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77) |
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#define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510) |
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+#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710) |
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+#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) |
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#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) |
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#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) |
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#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) |
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