/[packages]/updates/8/kernel/current/SOURCES/arm64-cpufeature-add-hwcap-for-feat_afp.patch
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Contents of /updates/8/kernel/current/SOURCES/arm64-cpufeature-add-hwcap-for-feat_afp.patch

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Revision 1789982 - (show annotations) (download)
Tue Mar 8 23:11:59 2022 UTC (2 years, 1 month ago) by tmb
File size: 4350 byte(s)
add current -stable queue
1 From foo@baz Tue Mar 8 08:47:19 PM CET 2022
2 From: Joey Gouly <joey.gouly@arm.com>
3 Date: Fri, 10 Dec 2021 16:54:30 +0000
4 Subject: arm64: cpufeature: add HWCAP for FEAT_AFP
5
6 From: Joey Gouly <joey.gouly@arm.com>
7
8 commit 5c13f042e73200b50573ace63e1a6b94e2917616 upstream.
9
10 Add a new HWCAP to detect the Alternate Floating-point Behaviour
11 feature (FEAT_AFP), introduced in Armv8.7.
12
13 Also expose this to userspace in the ID_AA64MMFR1_EL1 feature register.
14
15 Signed-off-by: Joey Gouly <joey.gouly@arm.com>
16 Cc: Will Deacon <will@kernel.org>
17 Acked-by: Marc Zyngier <maz@kernel.org>
18 Link: https://lore.kernel.org/r/20211210165432.8106-2-joey.gouly@arm.com
19 Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
20 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
21 ---
22 Documentation/arm64/cpu-feature-registers.rst | 9 +++++++++
23 Documentation/arm64/elf_hwcaps.rst | 4 ++++
24 arch/arm64/include/asm/hwcap.h | 1 +
25 arch/arm64/include/asm/sysreg.h | 1 +
26 arch/arm64/include/uapi/asm/hwcap.h | 1 +
27 arch/arm64/kernel/cpufeature.c | 2 ++
28 arch/arm64/kernel/cpuinfo.c | 1 +
29 7 files changed, 19 insertions(+)
30
31 --- a/Documentation/arm64/cpu-feature-registers.rst
32 +++ b/Documentation/arm64/cpu-feature-registers.rst
33 @@ -275,6 +275,15 @@ infrastructure:
34 | SVEVer | [3-0] | y |
35 +------------------------------+---------+---------+
36
37 + 8) ID_AA64MMFR1_EL1 - Memory model feature register 1
38 +
39 + +------------------------------+---------+---------+
40 + | Name | bits | visible |
41 + +------------------------------+---------+---------+
42 + | AFP | [47-44] | y |
43 + +------------------------------+---------+---------+
44 +
45 +
46 Appendix I: Example
47 -------------------
48
49 --- a/Documentation/arm64/elf_hwcaps.rst
50 +++ b/Documentation/arm64/elf_hwcaps.rst
51 @@ -251,6 +251,10 @@ HWCAP2_ECV
52
53 Functionality implied by ID_AA64MMFR0_EL1.ECV == 0b0001.
54
55 +HWCAP2_AFP
56 +
57 + Functionality implied by ID_AA64MFR1_EL1.AFP == 0b0001.
58 +
59 4. Unused AT_HWCAP bits
60 -----------------------
61
62 --- a/arch/arm64/include/asm/hwcap.h
63 +++ b/arch/arm64/include/asm/hwcap.h
64 @@ -106,6 +106,7 @@
65 #define KERNEL_HWCAP_BTI __khwcap2_feature(BTI)
66 #define KERNEL_HWCAP_MTE __khwcap2_feature(MTE)
67 #define KERNEL_HWCAP_ECV __khwcap2_feature(ECV)
68 +#define KERNEL_HWCAP_AFP __khwcap2_feature(AFP)
69
70 /*
71 * This yields a mask that user programs can use to figure out what
72 --- a/arch/arm64/include/asm/sysreg.h
73 +++ b/arch/arm64/include/asm/sysreg.h
74 @@ -896,6 +896,7 @@
75 #endif
76
77 /* id_aa64mmfr1 */
78 +#define ID_AA64MMFR1_AFP_SHIFT 44
79 #define ID_AA64MMFR1_ETS_SHIFT 36
80 #define ID_AA64MMFR1_TWED_SHIFT 32
81 #define ID_AA64MMFR1_XNX_SHIFT 28
82 --- a/arch/arm64/include/uapi/asm/hwcap.h
83 +++ b/arch/arm64/include/uapi/asm/hwcap.h
84 @@ -76,5 +76,6 @@
85 #define HWCAP2_BTI (1 << 17)
86 #define HWCAP2_MTE (1 << 18)
87 #define HWCAP2_ECV (1 << 19)
88 +#define HWCAP2_AFP (1 << 20)
89
90 #endif /* _UAPI__ASM_HWCAP_H */
91 --- a/arch/arm64/kernel/cpufeature.c
92 +++ b/arch/arm64/kernel/cpufeature.c
93 @@ -329,6 +329,7 @@ static const struct arm64_ftr_bits ftr_i
94 };
95
96 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
97 + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_AFP_SHIFT, 4, 0),
98 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0),
99 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0),
100 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0),
101 @@ -2465,6 +2466,7 @@ static const struct arm64_cpu_capabiliti
102 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE),
103 #endif /* CONFIG_ARM64_MTE */
104 HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),
105 + HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),
106 {},
107 };
108
109 --- a/arch/arm64/kernel/cpuinfo.c
110 +++ b/arch/arm64/kernel/cpuinfo.c
111 @@ -95,6 +95,7 @@ static const char *const hwcap_str[] = {
112 [KERNEL_HWCAP_BTI] = "bti",
113 [KERNEL_HWCAP_MTE] = "mte",
114 [KERNEL_HWCAP_ECV] = "ecv",
115 + [KERNEL_HWCAP_AFP] = "afp",
116 };
117
118 #ifdef CONFIG_COMPAT

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