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From 0296e09386fd0343150d04089291c1ee12db9b76 Mon Sep 17 00:00:00 2001 |
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From: Sasha Levin <sashal@kernel.org> |
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Date: Thu, 6 Jan 2022 17:53:31 -0600 |
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Subject: arm64: dts: agilex: use the compatible "intel,socfpga-agilex-hsotg" |
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From: Dinh Nguyen <dinguyen@kernel.org> |
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[ Upstream commit 268a491aebc25e6dc7c618903b09ac3a2e8af530 ] |
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The DWC2 USB controller on the Agilex platform does not support clock |
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gating, so use the chip specific "intel,socfpga-agilex-hsotg" |
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compatible. |
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|
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Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> |
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Signed-off-by: Sasha Levin <sashal@kernel.org> |
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--- |
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arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 4 ++-- |
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1 file changed, 2 insertions(+), 2 deletions(-) |
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|
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diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi |
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index 163f33b46e4f..de1e98c99ec5 100644 |
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--- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi |
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+++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi |
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@@ -502,7 +502,7 @@ |
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}; |
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usb0: usb@ffb00000 { |
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- compatible = "snps,dwc2"; |
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+ compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; |
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reg = <0xffb00000 0x40000>; |
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
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phys = <&usbphy0>; |
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@@ -515,7 +515,7 @@ |
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}; |
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|
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usb1: usb@ffb40000 { |
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- compatible = "snps,dwc2"; |
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+ compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; |
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reg = <0xffb40000 0x40000>; |
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interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
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phys = <&usbphy0>; |
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-- |
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2.34.1 |
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