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From 32807e38c3574bde659ef6ddf434e57c0d7cffe8 Mon Sep 17 00:00:00 2001 |
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From: Ian Romanick <ian.d.romanick@intel.com> |
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Date: Wed, 16 Mar 2022 12:56:54 -0700 |
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Subject: [PATCH 22/29] intel/fs: Force destination types on DP4A instructions |
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|
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Most of the time, this doesn't matter. On the versions with _sat, if |
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the destination type is incorrect, the clamping will not happen |
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correctly. |
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|
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Fixes the following CTS tests: |
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|
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dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.all_packed_ss_v4i8_out32 |
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dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.all_packed_su_v4i8_out32 |
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dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.all_packed_us_v4i8_out32 |
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dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.all_packed_uu_v4i8_out32 |
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dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.all_ss_v4i8_out32 |
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dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.all_su_v4i8_out32 |
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dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.all_us_v4i8_out32 |
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dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.all_uu_v4i8_out32 |
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dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.limits_packed_ss_v4i8_out32 |
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dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.limits_packed_su_v4i8_out32 |
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dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.limits_packed_us_v4i8_out32 |
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dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.limits_packed_uu_v4i8_out32 |
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dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.limits_ss_v4i8_out32 |
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dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.limits_su_v4i8_out32 |
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dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.limits_us_v4i8_out32 |
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dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.limits_uu_v4i8_out32 |
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dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.small_packed_ss_v4i8_out32 |
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dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.small_packed_su_v4i8_out32 |
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dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.small_packed_us_v4i8_out32 |
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dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.small_packed_uu_v4i8_out32 |
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dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.small_ss_v4i8_out32 |
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dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.small_su_v4i8_out32 |
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dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.small_us_v4i8_out32 |
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dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.small_uu_v4i8_out32 |
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|
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v2: Update anv-tgl-fails.txt. |
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|
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Reviewed-by: Ivan Briano <ivan.briano@intel.com> |
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Fixes: 0f809dbf404 ("intel/compiler: Basic support for DP4A instruction") |
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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15417> |
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(cherry picked from commit 19330eeb1d65c631ce11a0be1cb13437c6c28491) |
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--- |
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.pick_status.json | 2 +- |
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src/intel/compiler/brw_fs_nir.cpp | 6 +++--- |
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2 files changed, 4 insertions(+), 4 deletions(-) |
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|
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diff --git a/.pick_status.json b/.pick_status.json |
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index 283e3642175..03a0930b88a 100644 |
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--- a/.pick_status.json |
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+++ b/.pick_status.json |
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@@ -490,7 +490,7 @@ |
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"description": "intel/fs: Force destination types on DP4A instructions", |
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"nominated": true, |
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"nomination_type": 1, |
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- "resolution": 0, |
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+ "resolution": 1, |
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"main_sha": null, |
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"because_sha": "0f809dbf4048cbd89c5cf28dbb9ab38cc726fe2a" |
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}, |
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diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp |
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index 9376537bd44..e364c373210 100644 |
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--- a/src/intel/compiler/brw_fs_nir.cpp |
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+++ b/src/intel/compiler/brw_fs_nir.cpp |
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@@ -1886,7 +1886,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr, |
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|
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case nir_op_sdot_4x8_iadd: |
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case nir_op_sdot_4x8_iadd_sat: |
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- inst = bld.DP4A(result, |
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+ inst = bld.DP4A(retype(result, BRW_REGISTER_TYPE_D), |
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retype(op[2], BRW_REGISTER_TYPE_D), |
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retype(op[0], BRW_REGISTER_TYPE_D), |
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retype(op[1], BRW_REGISTER_TYPE_D)); |
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@@ -1897,7 +1897,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr, |
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|
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case nir_op_udot_4x8_uadd: |
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case nir_op_udot_4x8_uadd_sat: |
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- inst = bld.DP4A(result, |
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+ inst = bld.DP4A(retype(result, BRW_REGISTER_TYPE_UD), |
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retype(op[2], BRW_REGISTER_TYPE_UD), |
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retype(op[0], BRW_REGISTER_TYPE_UD), |
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retype(op[1], BRW_REGISTER_TYPE_UD)); |
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@@ -1908,7 +1908,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr, |
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|
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case nir_op_sudot_4x8_iadd: |
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case nir_op_sudot_4x8_iadd_sat: |
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- inst = bld.DP4A(result, |
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+ inst = bld.DP4A(retype(result, BRW_REGISTER_TYPE_D), |
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retype(op[2], BRW_REGISTER_TYPE_D), |
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retype(op[0], BRW_REGISTER_TYPE_D), |
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retype(op[1], BRW_REGISTER_TYPE_UD)); |
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-- |
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2.30.2 |
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